NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

Copying the Example

The source files for the example used in this tutorial are located in the following directory:

UNIX:

install_directory/tools/inca/tutorials/Intro_To_NCVerilog

Linux:

install_directory/tools/inca/tutorials/Intro_To_NCVerilog

Windows:

install_directory\tools\inca\tutorials\intro_to_ncverilog

Create a local directory and then copy the tutorial files into this local directory. This ensures that you have write access to your project directory while preserving the original contents of the tutorial files.

Preparing the Verilog Source Files for Simulation

The basic build process for the NC-Verilog simulator consists of two steps: parsing the Verilog source files with the ncvlog parser, and elaborating the design by invoking the ncelab elaborator on all top-level modules. After parsing the source files and elaborating the design, you can load the simulation snapshot into the ncsim simulator.

You can prepare your source files for simulation and load the snapshot into the simulator by using a single-step invocation method or by using a multi-step invocation method. Both invocation methods use the same build and simulation steps to serve the same purpose.

■Single step invocation (using the ncverilog program)

In single-step mode, you invoke a single program called ncverilog. The ncverilog program spawns the individual build steps as needed and then proceeds to simulation.

■Multi-step invocation

In multi-step mode, you invoke each of the three main programs (ncvlog, ncelab, and ncsim) separately. This multi-step process lets you have the finest control over the placement and reuse of intermediate files and the update process.

The invocation method that you use depends on a variety of factors, such as your current simulation environment, whether or not you want to modify this environment, whether or not users are using both the Verilog-XL and NC-Verilog simulators, and, perhaps most importantly, whether or not you want the NC-Verilog simulator to handle -y and -v technology libraries in exactly the same way that Verilog-XL handles those libraries.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

See the section called “Running the NC-Verilog Simulator” in the Cadence® NC-Verilog Simulator Help for an overview of the two invocation methods.

You can use either method for this tutorial, or you can explore both methods to determine which method is best for your environment.

Both methods require an OS shell window to work from. Open a shell window and change to the directory that contains the tutorial source files.

On UNIX or Linux, open a shell on your OS to run programs from the command line.

For the Verilog Desktop, open a command window by using the Start menu and then selecting Programs—Command Prompt.

Single-Step Invocation

You can compile, elaborate, and simulate your design with a single command line. This command line automatically runs the ncvlog, ncelab, and ncsim programs. The command that you use to run NC-Verilog in single-step invocation is called ncverilog.

The ncverilog program automatically creates everything that you need to run the NC-Verilog simulator, including all directories and libraries. It also automatically creates two required setup files if they do not already exist: a library definition file called cds.lib and a variables definition file called hdl.var. You can use Verilog-XL command-line options (for Verilog-XL users) and ncvlog, ncelab, and ncsim options on the ncverilog command line.

Creating the ncverilog Command Line

The syntax of the ncverilog command is as follows:

ncverilog verilog-xl_arguments [ncverilog_options]

Because Verilog simulation command lines often get very long, the command-line options and arguments are often stored in a text file, which you can then specify on the command line. With ncverilog, you specify the arguments file by using the -f option.

For this tutorial, a text file called rtl_xl.f has been created for you in your tutorial directory.

The contents of this file are as follows:

//File: rtl_xl.f

//Define variable names for conditional compilation. +define+memd +define+ram_init

+define+exp +define+no_trace +define+nob +define+DEMO

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

//Specify the directory to search for include files specified with ‘include in the

//Verilog source.

+incdir+include

//Disable some warning messages. +nowarnIWFA

+nowarnTFNPC

//Create a log file that has the specified name. -l rtl_xl.log

//Search the specified directory for unresolved Verilog cells. -y .

//When searching for unresolved Verilog cells, look in files that have the

//following extension. This option works in conjunction with the -y option.

+libext+.v

// Specify the top-level source file. dtmf_recvr_core_test.v

The following options are included in the rtl_xl.f argument file:

■+define+arg—Defines variable names that are used for conditional compilation.

■+incdir+arg—Defines the directory to search for include files specified with ’include in the Verilog source. In this example, the directory called include will be searched.

■+nowarnwarning_code—Suppresses the display of warning messages that have the specified message mnemonic.

■-l logfile_name—Specifies the name of the log file in which messages are stored.

■-y arg—Indicates the directory to search for unresolved Verilog cells. In this case, the tutorial directory itself will be searched for Verilog source that resolves these cells.

■+libext+.v—Specifies that files that have the extension .v in the directory specified by with the -y option and that match the module names of the unresolved cells will be used to resolve these cells.

The last argument in the arguments file is the top-level Verilog source file to be compiled.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

Use the following command to run the NC-Verilog simulator using single-step invocation:

ncverilog -f rtl_xl.f +nclinedebug +gui

The options used on the command line are:

■-f rtl_xl.f—Specifies the text file that contains command-line arguments.

■+nclinedebug—Enables support for setting line breakpoints and for single-stepping through source code. This option is translated to the ncvlog -linedebug option, and is required for the tutorial if you are running the NC-Verilog simulator. The -linedebug option impacts performance, so it should only be used when you want to debug the source code. For this reason, we have specified it on the command line instead of putting it in the arguments file.

Note: If you are running the Verilog Desktop simulator, all debug options are always on, so the -linedebug option is not available.

■+gui—Automatically invokes the simulator with the SimVision analysis environment.

When you run NC-Verilog using the command line shown above, the ncverilog program invokes the ncvlog parser to parse the source files, the ncelab elaborator to elaborate the design, and the ncsim simulator. Simulation stops at time 0 because of the +gui option.

You can now continue the tutorial with the information in the section called “Using the SimVision Analysis Environment” on page 11 .

Multi-Step Invocation

Before you can run the NC-Verilog simulator using the multi-step invocation method, you must create two setup files: a library definition file (cds.lib) and a variables definition file (hdl.var).

The cds.lib File

The cds.lib file is an ASCII text file that defines which libraries are accessible and where they are located. The file contains statements that map logical library names to their physical directory paths.

For this tutorial, you will define a library called worklib. Use any text editor to create the following cds.lib file and then save it in your tutorial directory.

DEFINE worklib ./worklib

Now create a directory or folder called worklib in the tutorial directory. This is the physical location of the library called worklib.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

See “The cds.lib File” in the Cadence® NC-Verilog Simulator Help for details on the cds.lib file.

The hdl.var File

The hdl.var file is an ASCII text file that contains the definition of variables that control tool behavior. One variable is the WORK variable, which you can use to specify the work library in which the compiler stores compiled objects and other derived data.

Use any text editor to create the following hdl.var file and then save it in your tutorial directory:

DEFINE WORK worklib

See “The hdl.var File” in the Cadence® NC-Verilog Simulator Help for details on the hdl.var file.

Compiling Verilog Source Files

The first step in performing a multi-step invocation of the NC-Verilog simulator is to compile your Verilog source code with ncvlog. This program performs syntactic and semantic checks on the source files and Verilog design units.

Invoke ncvlog with options and Verilog source file name(s). These arguments can appear in any order. Because the command line is often very long, you can store these command lines in a text file and then specify that file on the command line using the -f option. For this tutorial, a file called rtl.f has been created. The contents of this file are as follows:

//File: rtl.f

//Define variable names for conditional compilation. -define memd -define ram_init -define exp

-define no_trace -define nob -define DEMO

//Specify the directory to search for include files specified with ‘include in the

//Verilog source.

-incdir include

//Disable some warning messages. -nowarn IWFA -nowarn TFNPC

//Create a log file that has the specified name. -logfile rtl.log

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

//Print informative messages during compilation. -messages

//Specify the source files to compile.

dtmf_recvr_core_test.v accum_stat.v alu_32.v mult_32.v execute_i.v decode_i.v data_bus_mach.v port_bus_mach.v prog_bus_mach.v tdsp_core_glue.v tdsp_core_mach.v arb.v digit_reg.v data_sample_mux.v dma.v ram_128x16.v ram_256x16.v rom_512x16.v ram_128x16_test.v ram_256x16_test.v results_conv.v spi.v tdsp_core.v tdsp_data_mux.v tdsp_ds_cs.v test_control.v ulaw_lin_conv.v dtmf_recvr_core.v

The options specified in the rtl.f arguments file are:

■-define arg—Defines the variable names that are used for conditional compilation.

■-incdir arg—Defines the directory to search for include files specified with ’include in the Verilog source. In this example, the directory called include will be searched.

■-nowarn warning_code—Suppresses the display of warning messages that have the specified message mnemonic.

■-logfile logfile_name—Specifies the name of the log file in which messages are stored.

■-messages—Displays informative messages during compilation.

The remaining arguments are the Verilog source files to be compiled. Compile the source files with the following command:

ncvlog -f rtl.f -linedebug

There are two options used on this command line:

■-f rtl.f—Specifies the text file that contains command-line options and arguments.

■-linedebug—Enables support for setting line breakpoints and for single-stepping though source code. This option is required for the tutorial if you are running the

NC-Verilog simulator. The -linedebug option impacts performance, so it should only be used when you want to debug the source code. For this reason, we have specified it on the command line instead of putting it in the arguments file.

Note: If you are running the Verilog Desktop simulator, all debug options are always on, so the -linedebug option is not available.

NC-Verilog Simulator Tutorial

Cadence® NC-Verilog® Simulator Tutorial

As ncvlog runs, observe the text that is displayed. Notice the following line, which appears near the end of the compilation output text:

module worklib.test

All compiled Verilog design units are represented in this Library.Cell:View format. You will use this format to specify your design to the two downstream programs.

Elaborating the Design

After compiling the Verilog source code, you must elaborate the design using a program called ncelab.

The elaboration process constructs a design hierarchy based on the instantiation and configuration information in the design, establishes signal connectivity, and computes initial values for all objects in the design. This design hierarchy is stored in a simulation snapshot. The snapshot is the representation of your design that the simulator uses to run the simulation.

Invoke ncelab with command-line options and the Library.Cell:View name of the top-level HDL design unit. In this example, the top-level design unit is worklib.test:module.

ncelab -messages worklib.test:module -nowarn CSINFI

The -messages option displays informative messages during elaboration. The -nowarn option disables the warning message that has the specified mnemonic. In this example, the message with the code CSINFI ("implicit wire has no fanin") will be suppressed.

The worklib.test:module argument on the command line represents the compiled top-level design. The Library is represented by worklib, the Cell is represented by test, which is the module name of the design’s top-level testbench, and the View is represented by module. The default view in Verilog is either module or udp unless you specify something else at compile time.

After ncelab has elaborated the design, it writes the simulation snapshot. In this example, the snapshot is called worklib.test:module. Notice that the default snapshot name matches the syntax of the top-level design unit that you specified to ncelab. This is the name that you pass to the simulator.