8XC196Kx, Jx, CA USER’S MANUAL
The A/D converter uses a successive approximation algorithm to perform the analog-to-digital conversion. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors, and a 10-bit successive approximation register (SAR) with logic that guides the process. The resistive ladder provides 20 mV steps (VREF = 5.12 volts), while capacitive coupling creates 5 mV steps within the 20 mV ladder voltages. Therefore, 1024 internal reference voltage levels are available for comparison against the analog input to generate a 10-bit conversion result. In 8- bit conversion mode, only the resistive ladder is used, providing 256 internal reference voltage levels.
The successive approximation conversion compares a sequence of reference voltages to the analog input, performing a binary search for the reference voltage that most closely matches the input. The ½ full scale reference voltage is the first tested. This corresponds to a 10-bit result where the most-significant bit is zero and all other bits are ones (0111111111B). If the analog input was less than the test voltage, bit 10 of the SAR is left at zero, and a new test voltage of ¼ full scale (0011111111B) is tried. If the analog input was greater than the test voltage, bit 9 of SAR is set. Bit 8 is then cleared for the next test (0101111111B). This binary search continues until 10 (or 8) tests have occurred, at which time the valid conversion result resides in the AD_RESULT register where it can be read by software. The result is equal to the ratio of the input voltage divided by the analog supply voltage. If the ratio is 1.00, the result will be all ones.
11.4 PROGRAMMING THE A/D CONVERTER
The following A/D converter parameters are programmable:
• conversion input — input channel or test voltage (ANGND or V REF)
•zero-offset adjustment — no adjustment, plus 2.5 mV, minus 2.5 mV, or minus 5.0 mV
•conversion times — sample window time and conversion time for each bit
•operating mode — 8- or 10-bit conversion or 8-bit high or low threshold detection
•conversion trigger — immediate or EPA starts
This section describes the A/D converters’s registers and explains how to program them.
11-4
ANALOG-TO-DIGITAL CONVERTER
11.4.1 Programming the A/D Test Register
The AD_TEST register (Figure 11-2) selects either an analog input or a test voltage (ANGND or VREF) for conversion and specifies an offset voltage to be applied to the resistor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on VREF. With the results of these conversions, use a software routine to calculate the zero-offset error. Specify the zero-offset adjustment by writing the appropriate value to AD_TEST. This offset voltage is added to the resistor ladder and applies to all input channels. “Understanding A/D Conversion Errors” on page 11-14 describes zero-offset and other errors inherent in A/D conversions.
AD_TEST |
Address: |
1FAEH |
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Reset State: |
C0H |
The A/D test (AD_TEST) register enables conversions on ANGND and VREF and specifies adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND and one on VREF. With these results, a software routine can calculate the offset and gain errors.
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OFF1 |
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7:4 |
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Reserved; for compatibility with future devices, write zeros to these bits. |
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3:2 |
OFF1:0 |
Offset |
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These bits allows you to set the zero-offset point. |
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OFF1 OFF0 |
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no adjustment |
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add 2.5 mV |
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subtract 2.5 mV |
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subtract 5.0 mV |
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1 |
TV |
Test Voltage |
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This bit selects the test voltage for a test mode conversion. |
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1 |
= VREF |
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= ANGND |
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0 |
TE |
Test Enable |
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This bit determines whether normal or test mode conversions will be |
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performed. A normal conversion converts the analog signal input on one |
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of the analog input channels. A test conversion allows you to perform a |
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conversion on ANGND or VREF. |
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= test |
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= normal |
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Figure 11-2. A/D Test (AD_TEST) Register
11-5
8XC196Kx, Jx, CA USER’S MANUAL
11.4.2 Programming the A/D Result Register (for Threshold Detection Only)
To use the threshold-detection modes, you must first write a value to the high byte of AD_RESULT to set the desired reference (threshold) voltage.
AD_RESULT (Write) |
Address: |
1FAAH |
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Reset State: |
7F80H |
The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes.
15
REFV7 |
REFV6 |
REFV5 |
REFV4 |
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8
REFV3 REFV2 REFV1 REFV0
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REFV7:0 |
Reference Voltage |
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These bits specify the threshold value. This selects a reference voltage |
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that is compared with an analog input pin. When the voltage on the |
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analog input pin crosses over (detect high) or under (detect low) the |
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threshold value, the A/D interrupt flag is set. |
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Use the following formula to determine the value to write this register for |
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a given threshold voltage. |
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reference voltage = desired----------------------threshold--------------------------voltage---------------------×-----256-------- |
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VREF – ANGND |
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7:0 |
— |
Reserved; for compatibility with future devices, write zeros to these bits. |
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Figure 11-3. A/D Result (AD_RESULT) Register — Write Format
11.4.3 Programming the A/D Time Register
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy.
11-6
ANALOG-TO-DIGITAL CONVERTER
The AD_TIME register (Figure 11-4) specifies the A/D sample and conversion times. To avoid erroneous conversion results, use the TSAM and TCONV specifications on the datasheet to determine appropriate values.
AD_TIME |
Address: |
1FAFH |
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Reset State: |
FFH |
The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit.
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SAM2 |
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SAM0 |
CONV4 |
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CONV2 |
CONV1 |
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SAM2:0 |
A/D Sample Time |
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These bits specify the sample time. Use the following formula to |
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compute the sample time. |
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SAM = |
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where: |
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SAM |
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TSAM |
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FOSC |
= the XTAL1 frequency, in MHz |
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CONV4:0 |
A/D Convert Time |
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These bits specify the conversion time for each bit. Use the following |
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formula to compute the conversion time. |
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CONV |
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TCONV × FOSC – 3 |
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----------------------------------------------- |
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where: |
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2 × B |
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CONV= |
2 to 31 |
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TCONV = |
the conversion time, in μsec, from the data sheet |
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FOSC |
= the XTAL1 frequency, in MHz |
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B |
= the number of bits to be converted (8 or 10) |
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NOTES:
1.This register programs the speed at which the A/D can run — not the speed at which it can convert correctly. Consult the data sheet for recommended values.
2.Initialize the AD_TIME register before initializing the AD_COMMAND register.
3.Do not write to this register while a conversion is in progress; the results are unpredictable.
Figure 11-4. A/D Time (AD_TIME) Register
11-7