8XC196Kx, Jx, CA USER’S MANUAL

6.3BIDIRECTIONAL PORTS 1, 2, 5, AND 6

Although the bidirectional ports are very similar in both circuitry and configuration, port 5 differs from the others in some ways. Port 5, a memory-mapped port, uses a standard CMOS input buffer because of the high speeds required for system control functions. The remaining bidirectional ports use Schmitt-triggered input buffers for improved noise immunity.

NOTE

Ports 3 and 4 are significantly different from the other bidirectional ports. See “Bidirectional Ports 3 and 4 (Address/Data Bus)” on page 6-15 for details on the structure and operation of these ports.

Table 6-4 lists the bidirectional port pins with their special-function signals and associated peripherals.

Table 6-4. Bidirectional Port Pins

† This pin is not implemented on 8XC196Jx and 87C196CA devices.

†† This pin is not implemented on 8XC196Jx devices.

††† P5.4/SLPINT is not implemented on 8XC196Jx devices. P5.4 is implemented on the 87C196CA as a low-speed input/output pin (but it is not multiplexed with SLPINT).

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I/O PORTS

Table 6-4. Bidirectional Port Pins (Continued)

† This pin is not implemented on 8XC196Jx and 87C196CA devices.

†† This pin is not implemented on 8XC196Jx devices.

††† P5.4/SLPINT is not implemented on 8XC196Jx devices. P5.4 is implemented on the 87C196CA as a low-speed input/output pin (but it is not multiplexed with SLPINT).

Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control registers (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN register is a status register that returns the logic level present on the pins; it can only be read. The registers for the standard ports are byte-addressable and can be windowed. The port 5 registers must be accessed using 16-bit addressing and cannot be windowed. “Bidirectional Port Considerations” on page 6-12 discusses special considerations for reading P2_REG.7 and P6_REG.7:4.

Table 6-5. Bidirectional Port Control and Status Registers

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8XC196Kx, Jx, CA USER’S MANUAL

Table 6-5. Bidirectional Port Control and Status Registers (Continued)

6.3.1Bidirectional Port Operation

Figure 6-2 shows the logic for driving the output transistors, Q1 and Q2. Q1 can source at least –3 mA at V CC – 0.7 volts. Q2 can sink at least 3 mA at 0.45 volts. (Consult the datasheet for specifications.)

In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Table 6-6 is a logic table for I/O operation of these ports.

In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Special-function output signals clear SFDIR; special-function input signals set SFDIR. Table 6-7 is a logic table for special-function operation of these ports. Even if a pin is to be used in special-function mode, you must still initialize the pin as an input or output by writing to Px_DIR.

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I/O PORTS

Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer because of the high speeds required for system control functions. The signals are latched into the Px_PIN sample latch and output onto the internal bus when the Px_PIN register is read.

The falling edge of RESET# turns on transistor Q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset state. The active-low level of RESET# turns on transistor Q4, which weakly holds the pin high. (Q4 can source approximately –10 μA; consult the datasheet for exact specifications.) Q4 remains on, weakly holding the pin high, until your software writes to the Px_MODE register.

NOTE (8XC196CA, JQ, JR, JT, JV, KQ, KR)

P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal (half the crystal input frequency) rather than being held high. When CLKOUT is selected, it is always a complementary output.

6-7

Figure 6-2. Bidirectional Port Structure

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I/O PORTS

Table 6-6. Logic Table for Bidirectional Ports in I/O Mode

NOTES:

1.X = Don’t care.

2.If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off.

3.Px_PIN contains the current value on the pin.

4.During reset and until the first write to Px_MODE, Q3 is on.

Table 6-7. Logic Table for Bidirectional Ports in Special-function Mode

NOTES:

1.X = Don’t care.

2.If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off.

3.Px_PIN contains the current value on the pin.

4.During reset and until the first write to Px_MODE, Q3 is on.

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