SLAVE PORT

9.4.2Shared Memory Mode Example (8XC196KS and KT only)

In shared memory mode, the master and slave share a 256-byte block of memory. The high byte of the address (the base address) controls the location within the slave device memory space. The low byte of the address is always in the SLP_CMD register. The P3_REG register contains data to be read; the P3_PIN register contains the data written. This mode requires a multiplexed bus.

The primary difference between this mode and the standard slave mode is in the way that the address is loaded into the SLP_CMD register. The low byte of the address is automatically loaded into SLP_CMD on the falling edge of SLPALE. The data is latched on the rising edge of SLPRD# or SLPWR#. For this reason, a write or read operation requires only one master bus cycle rather than two and three bus cycles, respectively, in standard slave mode.

The time between the falling edge of SLPALE and the rising edge of SLPRD# is too short to allow the slave processor to perform the read. Therefore, reads are pipelined in this mode, as they are in standard slave mode. When the master requests a read operation, the data present during the current bus cycle is either “dummy” data or the data from the previous read operation. Alth ough read operations are pipelined, write operations are not. Therefore, write operations can be performed between reads without corrupting data that is waiting to be read. This allows the master to assign higher priority to write cycles. The master must wait for SLPINT to go high between reads or writes.

In this example, the master and slave share a 256-byte block of memory from 0400–04FFH.

9.4.2.1Master Device Program

In this mode, the master simply requests a read and receives data one bus cycle following the previous read. The following code segment illustrates how this is done.

The data that is read is actually the data from the previous read cycle. The address driven causes the slave to perform an interrupt service routine to fetch the data at that address. The data at the address is valid on the rising edge of SLPINT. Writing to the slave is equally simple, as the following code segment illustrates.

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8XC196Kx, Jx, CA USER’S MANUAL

9.4.2.2Slave Device Program

This example shows how the slave device reacts to reads and writes requested by the master. Regardless of the operation to be performed, the address is latched into the SLP_CMD register. The interrupt determines whether a read or write operation is to be performed.

An IBF interrupt requires a write operation. The slave branches to the IBF interrupt service routine, reads the data in the P3_PIN register, and writes that data to the address specified by adding a base address to the value in SLP_CMD. When the slave reads P3_PIN, it forces SLPINT high, which notifies the master that another operation can be performed.

An OBE interrupt requires a read operation. The slave branches to the OBE interrupt service routine, reads the data at the address specified by adding a base address to the value in SLP_CMD, and writes that data into the P3_REG register. When the slave writes the P3_REG register, it forces SLPINT high, which notifies the master that another operation can be performed. (Remember that read operations are pipelined.)

The following code segment shows the IBF and OBE interrupt service routines. The interrupt service routines are very much alike. One reads from the SFR space to the memory block; the other reads from the memory block to the SFR space. The slave need only know which routine to execute. The IBF and OBE interrupts must be enabled and interrupts must be globally enabled for these routines to function.

POPA

RET

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SLAVE PORT

9.4.2.3Multiplexed Bus Timings

The memory space required for the sample code is four bytes (two bytes for the address register, one for the temp register, and one for the base address). Reads and writes each require 58 state times (7.25 µs at 16 MHz). These times do not include interrupt latency (see “Inter rupt Latency” on page 5-7). They also do not include the master device bus cycle time. Each read or write operation requires only one master bus cycle. Figure 9-5 shows relative timing relationships. Consult the datasheet for actual timing specifications.

SLPCS#

SLPALE (Note 1)

SLPRD#

SLPINT (Note 2)

(Note 3)

Notes:

1.Connect to master's ALE signal.

2.The falling edge of SLPINT is the same for both standard and PTS interrupts. It follows the falling edge of SLPALE when SLPCS# is low. However, the rising edge of SLPINT occurs earlier for PTS interrupts than for standard.

3.Rising edge associated with either

–Read ready (write to P3_REG)

–Write complete (read of P3_PIN)

A0306-03

Figure 9-5. Standard or Shared Memory Mode Timings (Multiplexed Bus)

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