8XC196Kx, Jx, CA USER’S MANUAL

7.3.2.5Multiprocessor Communications

Modes 2 and 3 are provided for multiprocessor communications. In mode 2, the serial port sets the RI interrupt pending bit only when the ninth data bit is set. In mode 3, the serial port sets the RI interrupt pending bit regardless of the value of the ninth bit. The ninth bit is always set in address frames and always cleared in data frames.

One way to use these modes for multiprocessor communication is to set the master processor to mode 3 and the slave processors to mode 2. When the master processor wants to transmit a block of data to one of several slaves, it sends out an address frame that identifies the target slave. Because the ninth bit is set, an address frame interrupts all slaves. Each slave examines the address byte to check whether it is being addressed. The addressed slave switches to mode 3 to receive the data frames, while the slaves that are not addressed remain in mode 2 and are not interrupted.

7.4PROGRAMMING THE SERIAL PORT

To use the SIO port, you must configure the port pins to serve as special-function signals and set up the SIO channel.

7.4.1Configuring the Serial Port Pins

Before you can use the serial port, you must configure the associated port pins to serve as specialfunction signals. Table 7-1 on page 7-2 lists the pins associated with the serial port. Table 7-2 lists the port configuration registers, and Chapter 6, “I/O Ports,” explains how to configure the pins.

7.4.2Programming the Control Register

The SP_CON register (Figure 7-6) selects the communication mode and enables or disables the receiver, parity checking, and nine-bit data transmissions. Selecting a new mode resets the serial I/O port and aborts any transmission or reception in progress on the channel.

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SERIAL I/O (SIO) PORT

The serial port control (SP_CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission.

† This bit is reserved on the 87C196CA, 8XC196Jx, KQ, KR devices. For compatibility with future devices, write zero to this bit.

Figure 7-6. Serial Port Control (SP_CON) Register

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8XC196Kx, Jx, CA USER’S MANUAL

7.4.3Programming the Baud Rate and Clock Source

The SP_BAUD register (Figure 7-7) selects the clock input for the baud-rate generator and defines the baud rate for all serial I/O modes. This register acts as a control register during write operations and as a down-counter monitor during read operations.

WARNING

Writing to the SP_BAUD register during a reception or transmission can corrupt the received or transmitted data. Before writing to SP_BAUD, check the SP_STATUS register to ensure that the reception or transmission is complete.

The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.

The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using XTAL1 and 0001H when using T1CLK. In synchronous mode 0, the minimum BAUD_VALUE is 0001H for transmissions and 0002H for receptions.

† On the 87C196CA, 8XC196Jx devices the T1CLK pin is not implemented; therefore, on these devices this bit is reserved and should be written as one.

Figure 7-7. Serial Port Baud Rate (SP_BAUD) Register

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SERIAL I/O (SIO) PORT

The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.

The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum BAUD_VALUE is 0000H when using XTAL1 and 0001H when using T1CLK. In synchronous mode 0, the minimum BAUD_VALUE is 0001H for transmissions and 0002H for receptions.

† On the 87C196CA, 8XC196Jx devices the T1CLK pin is not implemented; therefore, on these devices this bit is reserved and should be written as one.

Figure 7-7. Serial Port Baud Rate (SP_BAUD) Register (Continued)

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