EVENT PROCESSOR ARRAY (EPA)

When hardware detects a pending EPAx interrupt, it sets the corresponding bit in EPA interrupt pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.

Figure 10-15. EPA Interrupt Pending 1 (EPA_PEND1) Registers

10.8 SERVICING THE MULTIPLEXED EPA INTERRUPT WITH SOFTWARE

The multiplexed interrupts (those represented by EPAx) should be serviced with a standard interrupt service routine rather than the PTS (Chapter 5, “Standard and PTS Interrupts”). The PTS can take only a limited number of actions, while interrupt service routines can be tailored to the needs of each interrupt.

The EPA_PEND (Figure 10-14) and EPA_PEND1 (Figure 10-15) registers contain the bits that identify the interrupt source(s). Traditionally, software would sort these bits to determine which interrupt service routine to execute. This sorting increases the overall interrupt response time by a significant number of states. However, the EPA interrupt priority vector register (EPAIPV, Figure 10-16) contains a number that corresponds to the highest-priority active interrupt source (Table 10-7).

For example, assume that an overrun occurs on capture/compare channel 9 and no other multiplexed interrupt is pending and unmasked. This sets the OVR9 pending bit in the EPA_PEND register. If the corresponding mask bit is set in the EPA_MASK register, the EPAx interrupt pending bit is set. If enabled, the EPAx interrupt is generated. The encoder places the number for the OVR9 interrupt (05H) into EPAIPV. Reading EPAIPV identifies capture/compare channel 9 as the source, clears the OVR9 pending bit, and clears EPAIPV. When the device vectors to the EPAx interrupt service routine, the EPAx pending bit is cleared. If other multiplexed interrupts have occurred, the encoder loads the number that corresponds to the highest-priority, active, multiplexed interrupt into EPAIPV. When the EPAIPV register contains 00H, there are no more pending interrupts associated with the EPAx interrupt. Thus, it is recommended that the EPAIPV register be read until it equals 00H to ensure that all pending, enabled interrupts are serviced.

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When an EPAx interrupt occurs, the EPA interrupt priority vector register (EPAIPV) contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 10-7).

EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPAx is activated. Reading EPAIPV clears the EPA pending bit for the interrupt associated with the value in EPAIPV. When all the EPA pending bits are cleared, the EPAx pending bit is also cleared.

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EVENT PROCESSOR ARRAY (EPA)

10.8.1 Using the TIJMP Instruction to Reduce Interrupt Service Overhead

The EPAIPV register and the TIJMP instruction can be used together to reduce the interrupt service overhead. The primary purpose of the TIJMP instruction is to reduce the interrupt response time associated with servicing multiplexed interrupts. With TIJMP, the additional time required to service interrupts is only the instruction time, 15 states. (See Appendix A for additional information about TIJMP.)

The format for the TIJMP instruction is TIJMP tbase,[index],#index_mask

TIJMP calculates the destination address as follows:

([index] AND #index_mask) × 2 + tbase

To use the TIJMP instruction in this application, you would create a jump table with 21 destination addresses; one for each of the 20 EPA interrupt sources and one for the return.

The following code is a simplified example of an interrupt service routine that uses the EPAIPV register with the TIJMP instruction to service an EPAx interrupt. This routine services all active interrupts in the EPA in order of their priority. The TIJMP instruction calculates an offset to fetch a word from a jump table (JTBASE in this example) which contains the start addresses of the interrupt service routines.

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This example assumes that EPAx is enabled, OVR0 is enabled, interrupts are globally enabled, and the capture/compare channel 0 has generated an OVR0 interrupt. This interrupt occurs when an edge is detected on the EPA channel and both the input buffer and EPA0_TIME are full. This causes software to enter the EPAx_ISR interrupt service routine.

Note that index_mask is set to 1FH . This sets the pointer to the end of the jump table to prevent software from jumping to an invalid address. Changing index_mask can dictate software control, thus superseding interrupt priorities.

Note that instead of a RET instruction at the end of OVR_EPA0_ISR, another TIJMP instruction is used. This is done to check for any other pending multiplexed interrupts. If EPAIPV contains a zero value (no pending interrupts) a vector to EPAx_DONE occurs and a RET is executed. This is to ensure that EPAIPV is cleared before the routine returns from the EPAx_ISR.

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