EVENT PROCESSOR ARRAY (EPA)
With this method, the resolution of the EPA (Figure 10-8 on page 10-18 and Figure 10-9 on page 10-19) determines the maximum PWM output frequency. (Resolution is the minimum time required between a capture or compare.) At 16 MHz, a 250 ns resolution results in a maximum PWM of 4 MHz.
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS
This section discusses configuring the port pins for the EPA and the timer/counters; describes how to program the timers, the capture/compare channels, and the compare-only channels; and explains how to enable the EPA interrupts.
10.5.1 Configuring the EPA and Timer/Counter Port Pins
Before you can use the EPA, you must configure the pins of port 1 and port 6 to serve as the spe- cial-function signals for the EPA and, optionally, for the timer/counter clock source and direction control signals. See “Bidirectional Ports 1, 2, 5, and 6” on page 6-4 for information about configuring the port pins.
NOTE
If you use T2CLK as the timer 2 input clock, you cannot use EPA capture/compare channel 0. If you use T2DIR as the timer 2 direction-control source, you cannot use EPA capture/compare channel 1.
Table 10-2 on page 10-3 lists the pins associated with the EPA and the timer/counters. Pins that are not being used for an EPA channel or timer/counter can be configured as standard I/O.
10.5.2 Programming the Timers
The control registers for the timers are T1CONTROL (Figure 10-8) and T2CONTROL (Figure 10-9). Write to these registers to configure the timers. Write to the TIMER1 and TIMER2 registers to load a specific timer value.
10-17
8XC196Kx, Jx, CA USER’S MANUAL
T1CONTROL |
Address: |
1F98H |
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Reset State: |
00H |
The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1.
7 |
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0 |
CE |
UD |
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M2 |
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M1 |
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M0 |
P2 |
P1 |
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P0 |
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Mnemonic |
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7 |
CE |
Counter Enable |
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This bit enables or disables the timer. From reset, the timers are |
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disabled and not free running. |
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0 |
= disables timer |
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1 |
= enables timer |
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6 |
UD |
Up/Down |
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This bit determines the timer counting direction, in selected modes (see |
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mode bits, M2:0) |
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0 |
= count down |
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1 |
= count up |
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5:3 |
M2:0 |
EPA Clock Direction Mode Bits |
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These bits determine the timer clocking source and direction control |
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source. |
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M2 |
M1 |
M0 |
Clock Source |
Direction Source |
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0 |
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0 |
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0 |
FOSC/4 |
UD bit (T1CONTROL.6) |
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X |
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0 |
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1 |
T1CLK Pin† |
UD bit (T1CONTROL.6)†† |
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0 |
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1 |
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0 |
F /4 |
T1DIR Pin†† |
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OSC |
T1DIR Pin†† |
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0 |
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1 |
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1 |
T1CLK Pin† |
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1 |
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1 |
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1 |
quadrature clocking using T1CLK and T1DIR pins†† |
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† |
If an external clock is selected, the timer counts on both the rising and |
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falling edges of the clock. |
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†† |
These modes are reserved on the 8XC196CA, Jx devices. |
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2:0 |
P2:0 |
EPA Clock Prescaler Bits |
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These bits determine the clock prescaler value. |
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P2 |
P1 |
P0 |
Prescaler |
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Resolution (at 16 MHz) |
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0 |
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0 |
divide by 1 (disabled) |
250 ns |
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0 |
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0 |
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1 |
divide by 2 |
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500 ns |
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0 |
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1 |
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0 |
divide by 4 |
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1 µs |
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0 |
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1 |
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1 |
divide by 8 |
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2 µs |
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1 |
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0 |
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0 |
divide by 16 |
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4 µs |
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1 |
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0 |
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1 |
divide by 32 |
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8 µs |
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1 |
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1 |
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0 |
divide by 64 |
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16 µs |
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1 |
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1 |
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1 |
reserved |
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— |
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Figure 10-8. Timer 1 Control (T1CONTROL) Register
10-18
EVENT PROCESSOR ARRAY (EPA)
T2CONTROL |
Address: |
1F9CH |
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Reset State: |
00H |
The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2.
7 |
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0 |
CE |
UD |
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M2 |
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M1 |
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M0 |
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P2 |
P1 |
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P0 |
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Bit |
Bit |
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Function |
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Number |
Mnemonic |
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7 |
CE |
Counter Enable |
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This bit enables or disables the timer. From reset, the timers are |
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disabled and not free running. |
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0 |
= disables timer |
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1 |
= enables timer |
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6 |
UD |
Up/Down |
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This bit determines the timer counting direction, in selected modes (see |
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mode bits, M2:0). |
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0 |
= count down |
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1 |
= count up |
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5:3 |
M2:0 |
EPA Clock Direction Mode Bits. |
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These bits determine the timer clocking source and direction source |
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M2 |
M1 |
M0 |
Clock Source |
Direction Source |
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0 |
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0 |
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0 |
FOSC/4 |
UD bit (T2CONTROL.6) |
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X |
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0 |
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1 |
T2CLK Pin† |
UD bit (T2CONTROL.6) |
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0 |
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1 |
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0 |
FOSC/4 |
T2DIR Pin |
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0 |
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1 |
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1 |
T2CLK Pin† |
T2DIR Pin |
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1 |
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0 |
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0 |
timer 1 overflow |
UD bit (T2CONTROL.6) |
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1 |
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1 |
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0 |
timer 1 |
same as timer 1 |
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1 |
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1 |
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1 |
quadrature clocking using T2CLK and T2DIR pins† |
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If an external clock is selected, the timer counts on both the rising and |
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falling edges of the clock. |
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2:0 |
P2:0 |
EPA Clock Prescaler Bits |
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These bits determine the clock prescaler value. |
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P2 |
P1 |
P0 |
Prescaler |
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Resolution (at 16 MHz) |
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0 |
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0 |
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0 |
divide by 1 (disabled) |
250 ns |
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0 |
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0 |
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1 |
divide by 2 |
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500 ns |
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0 |
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1 |
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0 |
divide by 4 |
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1 µs |
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0 |
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1 |
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1 |
divide by 8 |
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2 µs |
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1 |
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0 |
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0 |
divide by 16 |
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4 µs |
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1 |
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0 |
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1 |
divide by 32 |
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8 µs |
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1 |
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1 |
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0 |
divide by 64 |
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16 µs |
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1 |
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1 |
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1 |
reserved |
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— |
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Figure 10-9. Timer 2 Control (T2CONTROL) Register
10-19
8XC196Kx, Jx, CA USER’S MANUAL
10.5.3 Programming the Capture/Compare Channels
The EPAx_CON register controls the function of its assigned capture/compare channel. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit (RM), which is used to enable and disable remapping for high-speed PWM generation (see “Generating a High-speed PWM Output” on page 10-16). This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
To program a compare event, write to EPAx_CON (Figure 10-10) to configure the EPA capture/compare channel and then load the event time into EPAx_TIME. To program a capture event, you need only write to EPAx_CON. Table 10-6 shows the effects of various combinations of EPAx_CON bit settings.
Table 10-6. Example Control Register Settings and EPA Operations
Capture Mode
TB |
CE |
MODE |
RE |
AD |
ROT |
ON/RT |
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Operation |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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X |
0 |
0 |
0 |
— |
– |
— |
0 |
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None |
X |
0 |
0 |
1 |
— |
X |
X |
X |
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Capture on falling edges |
X |
0 |
1 |
0 |
— |
X |
X |
X |
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Capture on rising edges |
X |
0 |
1 |
1 |
— |
X |
X |
X |
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Capture on both edges |
X |
0 |
X |
1 |
— |
X |
1 |
X |
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Capture on falling edge and reset opposite timer |
X |
0 |
1 |
X |
— |
X |
1 |
X |
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Capture on rising edge and reset opposite timer |
X |
0 |
0 |
1 |
— |
1 |
X |
X |
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Start A/D conversion on falling edge |
X |
0 |
1 |
0 |
— |
1 |
X |
X |
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Start A/D conversion on rising edge |
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Compare Mode |
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TB |
CE |
MODE |
RE |
AD |
ROT |
ON/RT |
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Operation |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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X |
1 |
0 |
0 |
X |
— |
— |
0 |
None |
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X |
1 |
0 |
1 |
X |
X |
X |
X |
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Clear output pin |
X |
1 |
1 |
0 |
X |
X |
X |
X |
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Set output pin |
X |
1 |
1 |
1 |
X |
X |
X |
X |
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Toggle output pin |
X |
1 |
X |
X |
X |
X |
0 |
1 |
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Reset same timer |
X |
1 |
X |
X |
X |
X |
1 |
1 |
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Reset opposite timer |
X |
1 |
X |
X |
X |
1 |
X |
X |
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Start A/D conversion |
NOTES: — = bit is not used
X = bit may be used, but has no effect on the described operation. These bits cause other operations to occur.
10-20
EVENT PROCESSOR ARRAY (EPA)
EPAx_CON
x = 0–9 (8XC196K x)
x = 0–3, 8, 9 (8XC196CA, J x)
Address: |
1F60H + (x * 4) |
Reset State: |
F700H (x = 1 & 3) |
|
00H(x = 0, 2, 4–9) |
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
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15 |
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8 |
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x = 1, 3 |
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— |
— |
— |
— |
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— |
— |
RM |
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7 |
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0 |
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TB |
CE |
M1 |
M0 |
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RE |
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AD |
ROT |
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ON/RT |
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7 |
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0 |
x = 0, 2, 4–9 |
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TB |
CE |
M1 |
M0 |
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RE |
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AD |
ROT |
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ON/RT |
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Function |
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Number |
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Mnemonic |
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15:9† |
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— |
Reserved; always write as zeros. |
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8† |
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RM |
Remap Feature |
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The Remap feature applies to the compare mode of the EPA1 and EPA3 |
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only. |
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When the remap feature of EPA1 is enabled, EPA capture/compare |
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channel 0 shares output pin EPA1 with EPA capture/compare channel 1. |
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When the remap feature of EPA3 is enabled, EPA capture/compare |
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channel 2 shares output pin EPA3 with EPA capture/compare channel 3. |
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0 = remap feature disabled |
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1 = remap feature enabled |
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7 |
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TB |
Time Base Select |
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Specifies the reference timer. |
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0 = Timer 1 is the reference timer and Timer 2 is the opposite timer |
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1 = Timer 2 is the reference timer and Timer 1 is the opposite timer |
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A compare event (start of an A/D conversion; clearing, setting, or toggling |
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an output pin; and/or resetting either timer) occurs when the reference |
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timer matches the time programmed in the event-time register. |
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When a capture event (falling edge, rising edge, or an edge change on |
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the EPAx pin) occurs, the reference timer value is saved in the EPA event- |
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time register (EPAx_TIME). |
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† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers
10-21
8XC196Kx, Jx, CA USER’S MANUAL
EPAx_CON (Continued) x = 0–9 (8XC196K x)
x = 0–3, 8, 9 (8XC196CA, J x)
Address: |
1F60H + (x * 4) |
Reset State: |
F700H (x = 1 & 3) |
|
00H(x = 0, 2, 4–9) |
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
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15 |
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8 |
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x = 1, 3 |
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— |
— |
— |
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— |
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— |
— |
— |
RM |
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7 |
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0 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
ON/RT |
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7 |
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0 |
x = 0, 2, 4–9 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
ON/RT |
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Bit |
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Bit |
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Function |
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Mnemonic |
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6 |
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CE |
Compare Enable |
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Determines whether the EPA channel operates in capture or compare |
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mode. |
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0 = capture mode |
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1 = compare mode |
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5:4 |
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M1:0 |
EPA Mode Select |
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In capture mode, specifies the type of event that triggers an input capture. |
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In compare mode, specifies the action that the EPA executes when the |
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reference timer matches the event time. |
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M1 |
M0 |
Capture Mode Event |
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0 |
0 |
no capture |
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0 |
1 |
capture on falling edge |
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1 |
0 |
capture on rising edge |
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1 |
1 |
capture on either edge |
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M1 |
M0 |
Compare Mode Action |
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0 |
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no output |
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0 |
1 |
clear output pin |
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1 |
0 |
set output pin |
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1 |
1 |
toggle output pin |
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3 |
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RE |
Re-enable |
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Re-enable applies to the compare mode only. It allows a compare event |
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to continue to execute each time the event-time register (EPAx_TIME) |
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matches the reference timer rather than only upon the first time match. |
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0 = compare function is disabled after a single event |
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1 = compare function always enabled |
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† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)
10-22
EVENT PROCESSOR ARRAY (EPA)
EPAx_CON (Continued) x = 0–9 (8XC196K x)
x = 0–3, 8, 9 (8XC196CA, J x)
Address: |
1F60H + (x * 4) |
Reset State: |
F700H (x = 1 & 3) |
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00H(x = 0, 2, 4–9) |
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
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15 |
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8 |
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x = 1, 3 |
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RM |
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7 |
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0 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
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ON/RT |
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7 |
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0 |
x = 0, 2, 4–9 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
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ON/RT |
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Bit |
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Bit |
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Function |
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Number |
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Mnemonic |
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2 |
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AD |
A/D Conversion |
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Allows the EPA to start an A/D conversion that has been previously set up |
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in the A/D control registers. To use this feature, you must select the EPA |
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as the conversion source in the AD_CONTROL register. |
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0 = causes no A/D action |
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1 = EPA capture or compare event triggers an A/D conversion |
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1 |
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ROT |
Reset Opposite Timer |
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Controls different functions for capture and compare modes. |
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In Capture Mode: |
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0 = causes no action |
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1 = resets the opposite timer |
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In Compare Mode: |
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ROT selects the timer that is to be reset if the RT bit is set: |
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0 = selects base timer |
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1 = selects opposite timer |
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The TB bit (bit 7) selects which timer is the reference timer and which |
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timer is the opposite timer. |
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† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)
10-23
8XC196Kx, Jx, CA USER’S MANUAL
EPAx_CON (Continued) x = 0–9 (8XC196K x)
x = 0–3, 8, 9 (8XC196CA, J x)
Address: |
1F60H + (x * 4) |
Reset State: |
F700H (x = 1 & 3) |
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00H(x = 0, 2, 4–9) |
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3 have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
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15 |
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8 |
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x = 1, 3 |
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RM |
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7 |
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0 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
ON/RT |
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7 |
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0 |
x = 0, 2, 4–9 |
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TB |
CE |
M1 |
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M0 |
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RE |
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AD |
ROT |
ON/RT |
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Bit |
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Bit |
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Function |
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Number |
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Mnemonic |
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0 |
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ON/RT |
Overwrite New/Reset Timer |
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The ON/RT bit functions as overwrite new in capture mode and reset |
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timer in compare mode. |
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In Capture Mode (ON): |
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An overrun error is generated when an input capture occurs while the |
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event-time register (EPAx_TIME) and its buffer are both full. When an |
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overrun occurs, the ON bit determines whether old data is overwritten or |
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new data is ignored: |
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0 = ignores new data |
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1 = overwrites old data in the buffer |
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In Compare Mode (RT): |
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0 = disables the reset function |
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1 = resets the ROT-selected timer |
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† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)
10-24