EVENT PROCESSOR ARRAY (EPA)

The input frequency at which this occurs depends on the length of the interrupt service routine as well as other factors. Unless the interrupt service routine includes a check for overruns, this situation will remain the same until the device is reset or the EPAx_TIME register is read. The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME. This clears the buffer and allows another event to be captured. Remember that the act of the transferring the buffer contents to the EPAx_TIME register is what actually sets the EPAx interrupt pending bit and generates the interrupt.

Any one of the following methods can be used to prevent or recover from this situation.

•Clear EPAx_CON.0

When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to EPAx_TIME. This prevents the situation by ignoring new input capture events when both the capture buffer and EPAx_TIME contain valid capture times. The OVRx pending bit in EPA_PEND is set to indicate that an overrun occurred.

•Enable the OVRx interrupt and read the EPAx_TIME register within the ISR

If this situation occurs, the overrun (OVRx) interrupt will be generated. The OVRx interrupt will then be acknowledged and its interrupt service routine will read the EPAx_TIME register. After the CPU reads the EPAx_TIME register, the buffered data moves from the buffer to the EPAx_TIME register. This sets the EPA interrupt pending bit.

•Check for pending EPAx interrupts before exiting an EPAx ISR

Another method for avoiding this situation is to check for pending EPA interrupts before exiting the EPA interrupt service routine. This is an easy way to detect overruns and additional interrupts. It can also save loop time by eliminating the latency necessary to service the pending interrupt. However, this method cannot be used with the peripheral transaction server (PTS). If your system uses the PTS, you should choose one of the other methods.

10.4.2 Operating in Compare Mode

When the selected timer value matches the event-time value, the action specified in the control register occurs (i.e., the pin is set, cleared, toggled, or an A/D conversion is initiated). If the reenable bit (EPAx_CON.3 or COMPx_CON.3) is set, the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoccur until a new value is written to the eventtime register. See “Programming the Capture/Compare Channels” on page 10-20 and “Programming the Compare-only Channels” on page 10-25 for configuration information.

In compare mode, you can use the EPA to produce a pulse-width modulated (PWM) output. The following sections describe four possible methods.

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10.4.2.1Generating a Low-speed PWM Output

You can generate a low-speed, pulse-width modulated output with a single EPA channel and a standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle output, and the compare function re-enabled. Select standard interrupt service, enable the EPA interrupt, and globally enable interrupts with the EI instruction. When the assigned timer/counter value matches the value in the event-time register, the EPA toggles the output pin and generates an interrupt. The interrupt service routine loads a new value into EPAx_TIME.

The maximum output frequency depends upon the total interrupt latency and the interrupt-service execution times used by your system. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases. To determine the maximum, low-speed PWM frequency in your system, calculate your system's worst-case interrupt latency and worstcase interrupt-service execution time, and then add them together. The worst-case interrupt latency is the total latency of all the interrupts (both normal and PTS) used in your system. The worst-case interrupt-service execution time is the total execution time of all interrupt service routines and PTS routines.

The following example shows the calculations for a system that uses a single EPA channel, a single enabled interrupt, and the following interrupt service routine.

;If EPA0-3 interrupt is generated EPA0-3_ISR:

PUSHA

LD EPAx_CON, #toggle_command

ADD EPAx_TIME, TIMERx, [next_duty_ptr]; Load next event time POPA

RET

;If EPAx interrupt is generated from EPA4-9 interrupts EPAx_ISR:

;EPA4-9 service routines EPA4-9_ISR:

PUSHA

LD EPAx_CON, #toggle_command

ADD EPAx_TIME,TIMERx,[next_duty_ptr] LJMP EPAx_DONE

EPAx_DONE:

POPA

RET

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EVENT PROCESSOR ARRAY (EPA)

The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 5-9). To determine the execution time for an interrupt service routine, add up the execution time of the instructions in the ISR (Table A-9).

The total execution time for the ISR that services interrupts EPA3:0 is 79 state times for external stack usage or 71 state times for internal stack usage. Therefore, a single capture/compare channel 0–3 can be updated every 125 state times assuming internal stack us age (54 + 71). Each PWM period requires two updates (one setting and one clearing), so the execution time for a PWM period equals 250 state times. At 16 MHz, the PWM period is 31.25 µs and the maximum PWM frequency is 32 kHz.

The total execution time for the ISR that services the EPAx (capture/compare channels 4–9) interrupt is 175 state times for external stack usage or 159 for internal stack usage. Therefore, a single capture/compare channel 4–7 can be updated every 213 state times assuming internal stack usage (54 + 159). Each PWM period requires two updates (one setting and one clearing), so the execution time for a PWM period equals 426 state times. At 16 MHz, the PWM period is 53.25 µs and the maximum PWM frequency is 18.8 kHz.

10.4.2.2Generating a Medium-speed PWM Output

You can generate a medium-speed, pulse-width modulated output with a single EPA channel and the PTS set up in PWM toggle mode. “PWM Toggle Mode Example” on page 5-32 describes how to configure the EPA and PTS. Once started, this method requires no CPU intervention unless you need to change the output frequency. The method uses a single timer/counter. The timer/counter is not interrupted during this process, so other EPA channels can also use it if they do not reset it.

The maximum output frequency depends upon the total interrupt latency and interrupt-service execution time. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases. To determine the maximum, medium-speed PWM frequency in your system, calculate your system's worst-case interrupt latency and worst-case interrupt-service execution time, and then add them together. The worst-case interrupt latency is the total latency of all the interrupts (both normal and PTS) used in your system. The worst-case interrupt-service execution time is the total execution time of all interrupt service routines and PTS cycles.

The following example shows the calculations for a system that uses a single EPA channel, a single enabled interrupt, and PTS service. This example assumes that the PTS has been initialized, the duty cycle and frequency are fixed, and that the interrupt from the capture/compare channel is not multiplexed (i.e., EPA3:0).

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The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Interrupt Latency” on page 5-10). The PTS cycle execution time in PWM toggle mode is 15 state times (Table 5-4 on page 5-10). Therefore, a single capture/compare channel 0–3 can be updated every 58 state times (43 + 15). Each PWM period requires two updates (one setting and one clearing), so the execution time for a PWM period equals 116 state times. At 16 MHz, the PWM period is 14.49 µs and the maximum PWM frequency is 68.97 kHz.

10.4.2.3Generating a High-speed PWM Output

You can generate a high-speed, pulse-width modulated output with a pair of EPA channels and the PTS set up in PWM remap mode. “PWM Remap Mode Example” on page 5-37 describes how to configure the EPA and PTS. The remap bit (bit 8) must be set in EPA1_CON (to pair EPA0 and EPA1) or EPA3_CON (to pair EPA2 and EPA3). One channel must be configured to set the output; the other, to clear it. At the set (or clear) time, the PTS reads the old time value from EPAx_TIME, adds to it the PWM period constant, and returns the new value to EPAx_TIME. Set and clear times can be programmed to differ by as little as one timer count, resulting in very narrow pulses. Once started, this method requires no CPU intervention unless you need to change the output frequency. The method uses a single timer/counter. The timer/counter is not interrupted during this process, so other EPA channels can also use it if they do not reset it.

To determine the maximum, high-speed PWM frequency in your system, calculate your system's worst-case interrupt latency and then double it. The worst-case interrupt latency is the total latency of all the interrupts (both normal and PTS) used in your system. The following example shows the calculations for a system that uses a pair of remapped EPA channels (i.e., EPA0 and 1 or EPA 3 and 4), two enabled interrupts, and PTS service. This example assumes that the PTS has been initialized and that the duty cycle and frequency are fixed.

The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Interrupt Latency” on page 5-10). In this mode, the maximum period equals twice the PTS latency. Therefore, the execution time for a PWM period equals 86 state times. At 16 MHz, the PWM period is 10.75 µs and the maximum PWM frequency is 93 kHz.

10.4.2.4Generating the Highest-speed PWM Output

You can generate a highest-speed, pulse-width modulated output with a pair of EPA channels and a dedicated timer/counter. The first channel toggles the output when the timer value matches EPAx_TIME, and at some later time, the second channel toggles the output again and resets the timer/counter. This restarts the cycle. No interrupts are required, resulting in the highest possible speed. Software must calculate and load the appropriate EPAx_TIME values and load them at the correct time in the cycle in order to change the frequency or duty cycle.

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