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8XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf
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EVENT PROCESSOR ARRAY (EPA)

10.4.1 Operating in Capture Mode

In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register, which sets the EPA interrupt pending bit as shown in Figure 10-6. If enabled, an interrupt is generated. If a second event occurs before the CPU reads the first timer value in EPAx_TIME, the current timer value is loaded into the buffer and held there. After the CPU reads the EPAx_TIME register, the contents of the capture buffer are automatically transferred into EPAx_TIME and the EPA interrupt pending bit is set.

TIMERx

Event Occurs

at EPA Pin

Capture Buffer

EPA

Interrupt

Pending Bit

Set

EPAx_TIME

Read-out Time Value

A2458-02

Figure 10-6. EPA Simplified Input-Capture Structure

If a third event occurs before the CPU reads the event-time register, the overwrite bit (EPAx_CON.0) determines how the EPA will handle the event. If the bit is clear, the EPA ignores the third event. If the bit is set, the third event time overwrites the second event time in the capture buffer. Both situations set the overrun interrupt pending bit and, if enabled, generate an overrun interrupt. Table 10-5 summarizes the possible actions when a valid event occurs.

NOTE

In order for an event to be captured, the signal must be stable for at least two state times both before and after the transition occurs (Figure 10-7).

10-11

8XC196Kx, Jx, CA USER’S MANUAL

 

Event 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 State

 

2 State

 

 

 

 

 

 

 

 

 

Event 2

 

Times

 

Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 State

 

2 State

 

 

 

 

 

 

 

 

 

 

 

 

Times

 

Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3130-01

 

 

 

 

 

 

 

 

 

Figure 10-7. Valid EPA Input Events

 

Table 10-5. Action Taken when a Valid Edge Occurs

 

 

 

 

 

 

 

 

 

 

Overwrite Bit

Status of

 

 

 

 

 

 

 

 

Capture Buffer

 

 

 

 

Action taken when a valid edge occurs

(EPAx_CON.0)

 

 

 

 

& EPAx_TIME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

empty

 

Edge is captured and event time is loaded into the capture buffer and

 

 

 

EPAx_TIME register.

0

full

 

New data is ignored — no capture, EPA interrupt, or transfer occurs;

 

 

 

OVRx interrupt pending bit is set.

1

empty

 

Edge is captured and event time is loaded into the capture buffer and

 

 

 

EPAx_TIME register.

1

full

 

Old data is overwritten in the capture buffer; OVRx interrupt pending

 

 

 

bit is set.

 

 

 

 

An input capture event does not set the interrupt pending bit until the captured time value actually moves from the capture buffer into the EPAx_TIME register. If the buffer contains data and the PTS is used to service the interrupts, then two PTS interrupts occur almost back-to-back (that is, with one instruction executed between the interrupts).

10.4.1.1Handling EPA Overruns

Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA interrupt service routine. If no overrun handling strategy is in place, and if the following three conditions exist, a situation may occur where both the capture buffer and the EPAx_TIME register contain data, and no EPA interrupt is generated.

an input signal with a frequency high enough to cause overruns is present on an enabled EPA pin, and

the overwrite bit is set (EPAx_CON.0 = 1; old data is overwritten on overrun), and

the EPAx_TIME register is read at the exact instant that the EPA recognizes the captured edge as valid.

10-12

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