CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
Control applications often require high-speed event control. For example, the controller may need to periodically generate pulse-width modulated outputs, an analog-to-digital conversion, or an interrupt. In another application, the controller may monitor an input signal to determine the status of an external device. The event processor array (EPA) was designed to reduce the CPU overhead associated with these types of event control. This chapter describes the EPA and its timers and explains how to configure and program them.
10.1 EPA FUNCTIONAL OVERVIEW
The EPA performs input and output functions associated with two timer/counters, timer 1 and timer 2 (Figure 10-1). In the input mode, the EPA monitors an input pin for an event: a rising edge, a falling edge, or an edge in either direction. When the event occurs, the EPA records the value of the timer/counter, so that the event is tagged with a time. This is called an input capture. Input captures are buffered to allow two captures before an overrun occurs. In the output mode, the EPA monitors a timer/counter and compares its value with a value stored in a register. When the timer/counter value matches the stored value, the EPA can trigger an event: a timer reset or an output event (set a pin, clear a pin, toggle a pin, or take no action). This is called an output compare. The EPA sets an interrupt pending bit in response to an input capture or an output compare. This bit can optionally cause an interrupt. Table 10-1 lists the capture/compare and compare-only channels for each device in the 8XC196Kx family.
Table 10-1. EPA Channels
Device |
Capture/Compare Channels |
Compare-only Channels |
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87C196CA, 8XC196Jx |
EPA3:0 & EPA9:8 |
COMP1:0 |
8XC196Kx |
EPA9:0 |
COMP1:0 |
10-1
8XC196Kx, Jx, CA USER’S MANUAL
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Timer-Counter Unit |
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TIMER1 |
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TIMER2 |
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Capture/Compare |
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EPA 3:0 Interrupts |
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EPA 3:0 |
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Channel 0–3 |
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8XC196Kx Only |
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Capture/Compare |
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EPA7:4 |
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Channel 4–7 |
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Capture/Compare |
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EPA8 / COMP0 |
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Channel 8 |
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EPAx |
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Indirect |
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Interrupt |
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Compare-only |
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Interrupt |
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Channel 0 |
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Processor |
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Logic |
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Capture/Compare |
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EPA9 / COMP1 |
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Channel 9 |
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Compare-only
Channel 1
A3114-01
Figure 10-1. EPA Block Diagram
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS
Table 10-2 describes the EPA and timer/counter input and output signals. Each signal is multiplexed with a port pin as shown in the first column. Table 10-3 briefly describes the registers for the EPA capture/compare channels, EPA compare-only channels, and timer/counters.
10-2
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EVENT PROCESSOR ARRAY (EPA) |
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Table 10-2. EPA and Timer/Counter Signals |
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Port Pin |
EPA Signal(s) |
EPA |
Description |
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Signal Type |
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P1.0 |
EPA0 |
I/O |
High-speed input/output for capture/compare |
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channel 0. |
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T2CLK |
I |
External clock source for timer 2. If you use |
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T2CLK, you cannot use capture/compare channel |
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0. |
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P1.1 |
EPA1 |
I/O |
High-speed input/output for capture/compare |
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channel 1. |
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P1.2 |
EPA2 |
I/O |
High-speed input/output for capture/compare |
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channel 2. |
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T2DIR |
I |
External direction control for timer 2. If you use |
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T2DIR, you cannot use capture/compare channel |
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2. |
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P1.3 |
EPA3 |
I/O |
High-speed input/output for capture/compare |
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channel 3. |
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P1.7:4 |
EPA7:4† |
I/O |
High-speed input/output for capture/compare |
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channels 4–7. |
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P6.0 |
EPA8 |
I/O |
High-speed input/output for capture/compare |
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channel 8. |
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COMP0 |
O |
Output of the compare-only channel 0. |
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P6.1 |
EPA9 |
I/O |
High-speed input/output for capture/compare |
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channel 9. |
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COMP1 |
O |
Output of the compare-only channel 1. |
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P6.2 |
T1CLK† |
I |
External clock source for timer 1. |
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P6.3 |
T1DIR† |
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External direction control for timer 1. |
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† This pin is not implemented on the 8XC196Jx and 87C196CA devices.
Table 10-3. EPA Control and Status Registers
Mnemonic |
Address |
Description |
COMP0_CON |
1F88H |
EPAx Compare Control |
COMP1_CON |
1F8CH |
These registers control the functions of the compare-only |
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channels. |
COMP0_TIME |
1F8AH |
EPAx Compare Time |
COMP1_TIME |
1F8EH |
These registers contain the time at which an event is to occur on |
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the compare-only channels. |
EPA_MASK |
1FA0H |
EPA Interrupt Mask |
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The bits in this 16-bit register enable and disable (mask) 16 of the |
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interrupts associated with the EPAx interrupt, EPA4–9 and |
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OVR0–9. |
EPA_MASK1 |
1FA4H |
EPA Interrupt Mask 1 |
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The bits in this 8-bit register enable and disable (mask) four |
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interrupts associated with the EPAx interrupt, OVRTM1, |
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OVRTM2, COMP0, and COMP1 |
EPA_PEND |
1FA2H |
EPA Interrupt Pending |
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Any set bit in this register indicates a pending interrupt. |
10-3
8XC196Kx, Jx, CA USER’S MANUAL
Table 10-3. EPA Control and Status Registers (Continued)
Mnemonic |
Address |
Description |
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EPA_PEND1 |
1FA6H |
EPA Interrupt Pending 1 |
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Any set bit in this register indicates a pending interrupt. |
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EPA0_CON |
1F60H |
EPAx Capture/Compare Control |
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EPA1_CON |
1F64H |
These registers control the functions of the capture/compare |
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EPA2_CON |
1F68H |
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channels. EPA1_CON and EPA3_CON require an extra byte |
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EPA3_CON |
1F6CH |
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because they contain an additional bit for PWM remap mode. |
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EPA4_CON |
1F70H |
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These two registers must be addressed as words; the others can |
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EPA5_CON |
1F74H |
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be addressed as bytes. |
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EPA6_CON |
1F78H |
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EPA7_CON |
1F7CH |
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EPA8_CON |
1F80H |
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EPA9_CON |
1F84H |
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EPA0_TIME |
1F62H |
EPAx Capture/Compare Time |
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EPA1_TIME |
1F66H |
In capture mode, these registers contain the captured timer value. |
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EPA2_TIME |
1F6AH |
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In compare mode, these registers contain the time at which an |
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EPA3_TIME |
1F6EH |
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event is to occur. In capture mode, these registers are buffered to |
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EPA4_TIME |
1F72H |
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allow two captures before an overrun occurs. However, they are |
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EPA5_TIME |
1F76H |
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not buffered in compare mode. |
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EPA6_TIME |
1F7AH |
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EPA7_TIME |
1F7EH |
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EPA8_TIME |
1F82H |
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EPA9_TIME |
1F86H |
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EPAIPV |
1FA8H |
EPA Interrupt Priority Vector Register |
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The lower four bits of this register contain a number from 01H to |
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14H corresponding to the highest priority active EPAx interrupt |
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source. This value, when used with the TIJMP instruction, |
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enables software to branch to the correct interrupt service routine |
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for the active interrupt. |
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INT_MASK |
0008H |
Interrupt Mask |
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Five bits in this register enable and disable (mask) the individual |
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EPA0, EPA1, EPA2, and EPA3 interrupts and the multiplexed |
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EPAx interrupt. The EPA_MASK and EPA_MASK1 register bits |
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enable and disable the individual sources of the EPAx interrupt. |
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INT_PEND |
0009H |
Interrupt Pending |
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Five bits in this register are set to indicate pending individual |
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interrupts EPA0, EPA1, EPA2, and EPA3, and the multiplexed |
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EPAx interrupt. The EPA_PEND and EPA_PEND1 register bits |
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indicate which source(s) of the EPAx interrupt are pending. |
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P1_DIR |
1FD2H |
Port x Direction |
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P6_DIR |
1FD3H |
Each bit of Px_DIR controls the direction of the corresponding pin. |
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Clearing a bit configures a pin as a complementary output; setting |
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a bit configures a pin as an input or open-drain output. (Open- |
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drain outputs require external pull-ups.) |
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P1_MODE |
1FD0H |
Port x Mode |
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P6_MODE |
1FD1H |
Each bit of Px_MODE controls whether the corresponding pin |
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functions as a standard I/O port pin or as a special-function |
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signal. Setting a bit configures a pin as a special-function signal; |
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clearing a bit configures a pin as a standard I/O port pin. |
10-4
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EVENT PROCESSOR ARRAY (EPA) |
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Table 10-3. EPA Control and Status Registers (Continued) |
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Mnemonic |
Address |
Description |
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P1_PIN |
1FD6H |
Port x Input |
P6_PIN |
1FD7H |
Each bit of Px_PIN reflects the current state of the corresponding |
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pin, regardless of the pin configuration. |
P1_REG |
1FD4H |
Port x Data Output |
P6_REG |
1FD5H |
For an input, set the corresponding Px_REG bit. |
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For an output, write the data to be driven out by each pin to the |
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corresponding bit of Px_REG. When a pin is configured as |
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standard I/O (Px_MODE.x=0), the result of a CPU write to |
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Px_REG is immediately visible on the pin. When a pin is |
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configured as a special-function signal (Px_MODE.x=1), the |
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associated on-chip peripheral or off-chip component controls the |
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pin. The CPU can still write to Px_REG, but the pin is unaffected |
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until it is switched back to its standard I/O function. |
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This feature allows software to configure a pin as standard I/O |
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(clear Px_MODE.x), initialize or overwrite the pin value, then |
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configure the pin as a special-function signal (set Px_MODE.x). In |
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this way, initialization, fault recovery, exception handling, etc., can |
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be done without changing the operation of the associated |
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peripheral. |
T1CONTROL |
1F98H |
Timer 1 Control |
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This register enables/disables timer 1, controls whether it counts |
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up or down, selects the clock source and direction, and |
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determines the clock prescaler setting. |
T2CONTROL |
1F9CH |
Timer 2 Control |
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This register enables/disables timer 2, controls whether it counts |
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up or down, selects the clock source and direction, and |
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determines the clock prescaler setting. |
TIMER1 |
1F9AH |
Timer 1 Value |
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This register contains the current value of timer 1. |
TIMER2 |
1F9EH |
Timer 2 Value |
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This register contains the current value of timer 2. |
10-5