Processor A

Dual-port

Processor B

(Master)

RAM

(Slave)

(DPRAM)

Processor A

Slave

(Master)

On-chip

RAM

8XC196 Device

SLP_STAT.0

SLPINT/

P5.4

SLP_STAT.1

1.CON SLP

0.CON SLP

SLPALE

/P5.0

SLP_CON.2

SLP_CON

0

SLP_ADDR

1

SLP1/P3.1

D

Q

SLPRD#

/P5.3

SLPWR#

/P5.2

OE#

SLP_STAT

SLPCS#

OE#

P3_REG

P5.1

(Data Out)

WE#

P3_PIN

(Data In)

SLP7:0/

WE#

SLP_CMD

P3.7:0

Internal

Bus

8XC196 Device

A0267-03

Slave

Slave Port

Port Pin

Port

Description

Signal Type

Signal

P3.7:0

SLP7:0

I/O

Slave Port Address/Data bus

Slave port address/data bus in multiplexed mode and slave port

data bus in demultiplexed mode. In multiplexed mode, SLP1 is

the source of the internal control signal, SLP_ADDR.

P5.0

SLPALE

I

Slave Port Address Latch Enable

Functions as either a latch enable input to latch the value on

SLP1 (with a multiplexed address/data bus) or as the source of

the internal control signal, SLP_ADDR (with a demultiplexed

address/data bus).

P5.1

SLPCS#

I

Slave Port Chip Select

SLPCS# must be held low to enable slave port operation.

P5.2

SLPWR#

I

Slave Port Write Control Input

This active-low signal is an input to the slave. The rising edge of

SLPWR# latches data on port 3 into the P3_PIN or SLP_CMD

register.

SLPWR# is multiplexed with P5.2, WR#, and WRL#.

P5.3

SLPRD#

I

Slave Port Read Control Input

This active-low signal is an input to the slave. Data from the

P3_REG or SLP_STAT register is valid after the falling edge of

SLPRD#.

P5.4

SLPINT

O

Slave Port Interrupt

This active-high slave port output signal can be used to interrupt

the master processor.

NOTE: SLPINT is multiplexed with P5.4 and the ONCE# func-

tion (KR, KQ) or a special test-mode-entry pin (KS, KT).

Because driving this pin low on the rising edge of

RESET# could cause the device to enter a reserved

test mode, this pin should not be used as an input.

Mnemonic

Address

Description

INT_MASK

08H

Interrupt Mask

Setting bit 6 enables the output buffer empty (OBE) interrupt; clearing

the bit disables it.

Setting bit 7 enables the input buffer full (IBF) interrupt; clearing the bit

disables it.

INT_MASK1

13H

Interrupt Mask 1

Setting bit 0 enables the command buffer full (CBF) interrupt; clearing

the bit disables it.

INT_PEND

09H

Interrupt Pending

Bit 6, when set, indicates a pending output buffer empty (OBE) interrupt.

This bit is set after the master writes to the data input register, P3_PIN.

Mnemonic

Address

Description

INT_PEND1

12H

Interrupt Pending 1

Bit 0, when set, indicates a pending command buffer full (CBF) interrupt.

This bit is set after the master writes to the command register,

SLP_CMD.

P3_PIN

1FFEH

Slave Port Data Input Register

This register is also used for standard port 3 operation.

In slave port operation, this register accepts data written by the master

to be read by the slave. The slave can only read from this register and

the master can only write to it. If the master attempts to read from

P3_PIN, it will actually read P3_REG.

To write to this register in standard slave mode, the master must first

write “0” to the pin selected by SLP_CON.2. To write to this register in

shared memory mode (8XC196KS and KT only), the master must first

write “0” to the SLP1 pin.

P3_REG

1FFCH

Slave Port Data Output Register

This register is also used for standard port 3 operation.

In slave port operation, this register accepts data written by the slave to

be read by the master. The slave can write to and read from this register.

The master can only read it. If the master attempts to write to this

register, it will actually write to P3_PIN.

To read from this register in standard slave mode, the master must first

write “0” to the pin selected by SLP_CON.2. To read from this register in

shared memory mode (8XC196KS and KT only), the master must first

write “0” to the SLP1 pin.

SLP_CMD

1FFAH

Slave Port Command Register

This register accepts commands from the master to the slave. The

commands are defined by the device software. The slave can read from

and write to this register. The master can only write to it.

To write to this register in standard slave mode, the master must first

write “1” to the pin selected by SLP_CON.2. To write to this register in

shared memory mode (8XC196KS and KT only), the master must first

write “1” to the SLP1 pin.

SLP_CON

1FFBH

Slave Port Control Register

This register is used to configure the slave port. It selects the operating

mode (8XC196KS and KT only), enables and disables slave port

operation, controls whether the master accesses the data registers or

the control and status registers, and controls whether the SLPINT signal

is asserted when the input buffer empty (IBE) and output buffer full

(OBF) flags are set in the SLP_STAT register. Only the slave can access

this register.

SLP_STAT

1FF8H

Slave Port Status Register

The master can read this register to determine the status of the slave.

The slave can read all bits. If the master attempts to write to SLP_STAT,

it actually writes to SLP_CMD. To read from this register in standard

slave mode, the master must first write “1” to the pin selected by

SLP_CON.2. To read from this register in shared memory mode

(8XC196KS and KT only), the master must first write “1” to the SLP1

pin.