CHAPTER 8 SYNCHRONOUS SERIAL I/O (SSIO) PORT

8XC196Kx, Jx, CA USER’S MANUAL

8.2SSIO PORT SIGNALS AND REGISTERS

Table 8-1 describes the SSIO signals and Table 8-2 describes the control and status registers.

Table 8-2. SSIO Port Control and Status Registers

NOTE: Always write zeros to the reserved bits in these registers.

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NOTE: Always write zeros to the reserved bits in these registers.

8.3SSIO OPERATION

Each SSIO channel can be configured as either master or slave and as either transmitter or receiver, allowing the channels to communicate in several bidirectional, single-byte transfer modes (Figure 8-2). A master device transmits a clock signal; a slave device receives a clock signal.

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Figure 8-2. SSIO Operating Modes

•One channel can act as master transceiver to communicate with compatible protocols in half-duplex mode. This mode requires one data input/output pin and one clock output pin.

•One channel can act as slave transceiver to communicate with compatible protocols in halfduplex mode. This mode requires one data input/output pin and one clock input pin.

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SYNCHRONOUS SERIAL I/O (SSIO) PORT

•The two channels can operate together, from the same clock, as master transceivers to communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires one data input pin, one data output pin, and two clock pins (the clock output pin from one channel connected to the clock input pin of the other).

•The two channels can operate together, from the same clock, as slave transceivers to communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires one data input pin, one data output pin, and two clock input pins.

•The two channels can operate independently, with different clocks, to communicate in nonlockstep, full-duplex mode. In this mode, one channel acts as slave (receives a clock) and the other acts as master (transmits a clock). This mode requires a data input pin, a data output pin, a clock input pin, and a clock output pin.

The SSIO channels can also operate in handshaking modes for unidirectional, multi-byte transfers. These modes enable a master device to perform SSIO transfers using the PTS. Handshaking prevents a data underflow or overflow from occurring at the slave. It takes place in hardware, using the clock pins, with no CPU overhead.

•The two channels can operate with handshaking enabled, in full-duplex mode. One channel acts as slave and the other acts as master. This mode requires four pins.

•The two channels can operate with handshaking enabled, in half-duplex mode. One channel acts as slave and the other acts as master. This mode requires two pins.

Each channel contains an 8-bit buffer register, SSIOx_BUF, and logic to clock the data into and out of the transceiver. In receive mode, data is shifted (MSB first) from the SDx pin into SSIOx_BUF. In transmit mode, data is shifted from SSIOx_BUF onto the SDx pin. The receiver latches data from the transmitter on the rising edge of SCx and the transmitter changes (or floats) output data on the falling edge of SCx.

In the handshaking modes, the clock polarities are reversed, so the corresponding clock edges are also reversed. The clock pin, SCx, must be configured as an open-drain output in both master and slave modes. (This configuration requires an external pull-up.) The master leaves the SCx output high at the end of each byte transfer. The slave pulls its clock input low when it is busy. (In receive mode, the slave is busy when the buffer is full; in transmit mode, the slave is busy when the buffer is empty.) The slave releases SCx when it is ready to receive or transmit. The master waits for SCx to return high before attempting the next transfer. Figure 8-3 illustrates transmit and receive timings with and without handshaking.

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