8XC196Kx, Jx, CA USER’S MANUAL
6.3.2Bidirectional Port Pin Configurations
Each bidirectional port pin can be individually configured to operate either as an I/O pin or as a pin for a special-function signal. In the special-function configuration, the signal is controlled by an on-chip peripheral or an off-chip component. In either configuration, two modes are possible:
•complementary output (output only)
•high-impedance input or open-drain output (input, output, or bidirectional)
To prevent the CMOS inputs from floating, the bidirectional port pins are weakly pulled high during and after reset, until your software writes to Px_MODE. The default values of the control registers after reset configure the pins as high-impedance inputs with weak pull-ups. To ensure that the ports are initialized correctly and that the weak pull-ups are turned off, follow this suggested initialization sequence:
1.Write to Px_DIR to establish the individual pins as either inputs or outputs. (Outputs will drive the data that you specify in step 3.)
— For a complementary output, clear its P x_DIR bit.
—For a high-impedance input or an open-drain output, set its P x_DIR bit. (Open-drain outputs require external pull-ups.)
2.Write to Px_MODE to select either I/O or special-function mode. Writing to Px_MODE (regardless of the value written) turns off the weak pull-ups. Even if the entire port is to be used as I/O (its default configuration after reset), you must write to Px_MODE to ensure that the weak pull-ups are turned off.
—For a standard I/O pin, clear its P x_MODE bit. In this mode, the pin is driven as defined in steps 1 and 3.
—For a special-function signal, set its P x_MODE bit. In this mode, the associated peripheral controls the pin.
3.Write to Px_REG.
—For output pins defined in step 1, write the data that is to be driven by the pins to the corresponding Px_REG bits. For special-function outputs, the value is immaterial because the peripheral controls the pin. However, you must still write to Px_REG to initialize the pin.
— For input pins defined in step 1, set the corresponding P x_REG bits.
Table 6-8 lists the control register values for each possible configuration. For special-function outputs, the Px_REG value is immaterial (don’t care) because the associated peripheral controls the pin in special-function mode. However, you must still write to Px_REG to initialize the pin. For a bidirectional pin to function as an input (either special function or port pin), you must set Px_REG.
6-10
I/O PORTS
Table 6-8. Control Register Values for Each Configuration
Desired Pin Configuration |
Configuration Register Settings |
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Standard I/O Signal |
Px_DIR |
Px_MODE † |
Px_REG |
Complementary output, driving 0 |
0 |
0 |
0 |
Complementary output, driving 1 |
0 |
0 |
1 |
Open-drain output, strongly driving 0 |
1 |
0 |
0 |
Open-drain output, high-impedance |
1 |
0 |
1 |
Input |
1 |
0 |
1 |
Special-function signal |
Px_DIR |
Px_MODE † |
Px_REG |
Complementary output, output value controlled by peripheral |
0 |
1 |
X |
Open-drain output, output value controlled by peripheral |
1 |
1 |
X |
Input |
1 |
1 |
1 |
† During reset and until the first write to Px_MODE, the pins are weakly held high.
6.3.3Bidirectional Port Pin Configuration Example
Assume that you wish to configure the pins of a bidirectional port as shown in Table 6-9.
Table 6-9. Port Configuration Example
Port Pin(s) |
Configuration |
Data |
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Px.0, Px.1 |
high-impedance input |
high-impedance |
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Px.2, Px.3 |
open-drain output |
0 |
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Px.4 |
open-drain output |
1 (assuming external pull-up) |
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Px.5, Px.6 |
complementary output |
0 |
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Px.7 |
complementary output |
1 |
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To do so, you could use the following example code segment. Table 6-10 shows the state of each pin after reset and after execution of each line of the example code.
LDB Px_DIR,#00011111B
LDB Px_MODE,#00000000B
LDB Px_REG,#10010011B
6-11
8XC196Kx, Jx, CA USER’S MANUAL
Table 6-10. Port Pin States After Reset and After Example Code Execution
Action or Code |
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Resulting Pin States† |
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Px.7 |
Px.6 |
Px.5 |
Px.4 |
Px.3 |
Px.2 |
Px.1 |
Px.0 |
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Reset |
wk1 |
wk1 |
wk1 |
wk1 |
wk1 |
wk1 |
wk1 |
wk1 |
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LDB Px_DIR, #00011111B |
1 |
1 |
1 |
wk1 |
wk1 |
wk1 |
wk1 |
wk1 |
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LDB Px_MODE, #00000000B |
1 |
1 |
1 |
HZ1 |
HZ1 |
HZ1 |
HZ1 |
HZ1 |
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LDB Px_REG, #10010011B |
1 |
0 |
0 |
HZ1 |
0 |
0 |
HZ1 |
HZ1 |
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† wk1 = weakly pulled high, HZ1 = high impedance (actually a “1” with an external pull-up).
6.3.4Bidirectional Port Considerations
This section outlines special considerations for using the pins of these ports.
Port 1 |
After reset, your software must configure the device to match the |
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external system. This is accomplished by writing appropriate config- |
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uration data into P1_MODE. Writing to P1_MODE not only |
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configures the pins but also turns off the transistor that weakly holds |
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the pins high (Q4 in Figure 6-2 on page 6-8). For this reason, even if |
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port 1 is to be used as it is configured at reset, you should still write |
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data into P1_MODE. |
Port 2 |
After reset, your software must configure the device to match the |
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external system. This is accomplished by writing appropriate config- |
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uration data into P2_MODE. Writing to P2_MODE not only |
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configures the pins but also turns off the transistor that weakly holds |
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the pins high (Q4 in Figure 6-2 on page 6-8). For this reason, even if |
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port 2 is to be used as it is configured at reset, you should still write |
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data into P2_MODE. |
P2.2/EXTINT |
Writing to P2_MODE.2 sets the EXTINT interrupt pending bit. After |
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configuring the port pins, clear the interrupt pending register before |
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enabling interrupts. See “Design Considerations for External |
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Interrupt Inputs” on page 6-15. |
P2.5/HOLD# |
8XC196Kx Only: If P2.5 is configured as a standard I/O port pin, |
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the device does not recognize signals on this pin as HOLD#. Instead, |
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the bus controller receives an internal HOLD signal. This enables the |
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device to access the external bus while it is performing I/O at P2.5. |
6-12
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I/O PORTS |
P2.6/HLDA# |
The HLDA# pin is used in systems with more than one processor |
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using the system bus. This device asserts HLDA# to indicate that it |
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has freed the bus in response to HOLD# and another processor can |
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take control. (This signal is active low to avoid misinterpretation by |
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external hardware immediately after reset.) |
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P2.6/HLDA# is the enable pin for ONCE mode in certain 8XC196Kx |
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devices (see Chapter 14, “Special Operating Modes”) and one of the |
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enable pins for Intel-reserved test modes. Because a low input during |
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reset could cause the device to enter ONCE mode or a reserved test |
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mode, exercise caution if you use this pin for input. Be certain that |
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your system meets the VIH specification (listed in the datasheet) |
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during reset to prevent inadvertent entry into ONCE mode or a test |
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mode. |
P2.7/CLKOUT |
8XC196CA, JQ, JR, JT, JV, KQ, KR: Following reset, P2.7 carries |
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the strongly driven CLKOUT signal. It is not held high. When P2.7 |
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is configured as CLKOUT, it is always a complementary output. |
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8XC196KS, KT: Following reset, P2.7 is weakly held high. |
P2.7 |
A value written to the upper bit of P2_REG (bit 7) is held in a buffer |
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until the corresponding P2_MODE bit is cleared, at which time the |
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value is loaded into the P2_REG bit. A value read from P2_REG.7 is |
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the value currently in the register, not the value in the buffer. |
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Therefore, any change to P2_REG.7 can be read only after |
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P2_MODE.7 is cleared. |
Port 5 |
After reset, the device configures port 5 to match the external system. |
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The following paragraphs describe the states of the port 5 pins after |
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reset and until your software writes to the P5_MODE register. |
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Writing to P5_MODE not only configures the pins but also turns off |
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the transistor that weakly holds the pins high (Q4 in Figure 6-2 on |
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page 6-8). For this reason, even if port 5 is to be used as it is |
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configured at reset, you should still write data into P5_MODE. |
P5.0/ALE |
If EA# is high on reset (internal access), the pin is weakly held high |
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until your software writes to P5_MODE. If EA# is low on reset |
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(external access), either ALE or ADV# is activated as a system |
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control pin, depending on the ALE bit of CCR0. In either case, the |
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pin becomes a true complementary output. |
P5.1/INST |
8XC196Kx Only: This pin remains weakly held high until your |
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software writes configuration data into P5_MODE. |
P5.2/WR#/WRL# |
This pin remains weakly held high until your software writes config- |
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uration data into P5_MODE. |
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6-13 |
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8XC196Kx, Jx, CA USER’S MANUAL
P5.3/RD# |
If EA# is high on reset (internal access), the pin is weakly held high |
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until your software writes to P5_MODE. If EA# is low on reset |
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(external access), RD# is activated as a system control pin and the |
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pin becomes a true complementary output. |
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P5.4/SLPINT |
8XC196Kx Only: This pin is weakly held high until your software |
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writes to P5_MODE. P5.4/SLPINT is the enable pin for ONCE mode |
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in certain 8XC196Kx devices (see Chapter 14, “Special Operating |
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Modes”) and one of the enable pins for Intel-reserved test modes. |
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Because a low input during reset could cause the device to enter |
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ONCE mode or a reserved test mode, exercise caution if you use this |
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pin for input. Be certain that your system meets the VIH specification |
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(listed in the datasheet) during reset to prevent inadvertent entry into |
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ONCE mode or a test mode. |
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P5.5/BHE#/WRH# |
This pin is weakly held high until the CCB fetch is completed. At |
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that time, the state of this pin depends on the value of the BW0 bit of |
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the CCRs. If BW0 is clear, the pin remains weakly held high until |
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your software writes to P5_MODE. If BW0 is set, BHE# is activated |
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as a system control pin and the pin becomes a true complementary |
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output. |
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P5.6/READY |
8XC196CA, Kx Only: This pin remains weakly held high until the |
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CCB fetch is completed. At that time, the state of this pin depends on |
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the value of the IRC0–IRC2 bits of the CCRs. If IRC0–IRC2 are all |
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set (111B), READY is activated as a system control pin. This |
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prevents the insertion of infinite wait states upon the first access to |
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external memory. For any other values of IRC0–IRC2, the pin is |
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configured as I/O upon reset. |
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NOTE |
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If IRC0–IRC2 of the CCB are all set (activating READY as a |
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system control pin) and P5_MODE.6 is cleared (configuring |
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the pin as I/O), an external memory access may cause the |
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processor to lock up. |
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P5.7/BUSWIDTH |
8XC196Kx Only: This pin remains weakly held high until your |
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software writes configuration data into P5_MODE. |
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P6.0–P6.7 |
After reset, your software must configure the device to match the |
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external system. This is accomplished by writing appropriate config- |
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uration data into P6_MODE. Writing to P6_MODE not only |
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configures the pins but also turns off the transistor that weakly holds |
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the pins high (Q4 in Figure 6-2 on page 6-8). For this reason, even if |
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port 6 is to be used as it is configured at reset, you should still write |
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data into P6_MODE. |
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6-14 |
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