8XC196Kx, Jx, CA USER’S MANUAL

When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

† Bit 7 is reserved on the 8XC196Jx devices, bit 5 is reserved on the 8XC196Jx, Kx devices, and bit 0 is reserved on the 87C196CA, 8XC196Jx devices. For compatibility with future devices, always write zeros to these bits.

Figure 5-8. Interrupt Pending 1 (INT_PEND1) Register

5.6INITIALIZING THE PTS CONTROL BLOCKS

Each PTS interrupt requires a block of data called the PTS control block (PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up the specific parameters for the routine. You must set up the PTSCB for each interrupt source before enabling the corresponding PTS interrupts.

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STANDARD AND PTS INTERRUPTS

Each PTS control block (PTSCB) requires eight data bytes in register RAM. The address of the first (lowest) byte is stored in the PTS vector table in special-purpose memory (see “Special-pur- pose Memory” on page 4-3). Figure 5-9 shows the PTSCB for each PTS mode. Unused PTSCB bytes can be used as extra RAM.

NOTE

The PTSCB must be located in register RAM. The location of the first byte of the PTSCB must be aligned on a quad-word boundary (an address evenly divisible by 8).

Figure 5-9. PTS Control Blocks

5.6.1Specifying the PTS Count

For single transfer, block transfer, and A/D scan routines, the first location of the PTSCB contains an 8-bit value called PTSCOUNT. This value defines the number of interrupts that will be serviced by the PTS routine. The PTS decrements PTSCOUNT after each PTS cycle. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit (Figure 5-10), which requests an end-of-PTS interrupt. The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appropriate PTSSEL bit to re-enable PTS interrupt service.

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8XC196Kx, Jx, CA USER’S MANUAL

The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set manually to re-enable the PTS channel.

1.Bit 13 is reserved on the 8XC196Jx, Kx devices and bits 6–8 are reserved on the 87C196CA, 8XC196Jx devices. For compatibility with future devices, write zeros to these bits.

Figure 5-10. PTS Service (PTSSRV) Register

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STANDARD AND PTS INTERRUPTS

5.6.2Selecting the PTS Mode

The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTS mode (Figure 5-11). The function of bits 0–4 differ for each PTS mode. Refer to the sections that describe each routine in detail to see the function of these bits. Table 5-4 on page 5-10 lists the execution times for each PTS mode.

† The function of this bit depends upon which mode is selected. See the PTS control block description in each PTS mode section.

Figure 5-11. PTS Mode Selection Bits (PTSCON Bits 7:5)

5.6.3Single Transfer Mode

In single transfer mode, an interrupt causes the PTS to transfer a single byte or word (selected by the BW bit in PTSCON) from one memory location to another. This mode is typically used with serial I/O, or synchronous serial I/O, or slave port interrupts. It can also be used with the EPA to move captured time values from the event-time register to internal RAM for further processing. See AP-445, 8XC196KR Peripherals: A User’s Point of View, for application examples with code. Figure 5-12 shows the PTS control block for single transfer mode.

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8XC196Kx, Jx, CA USER’S MANUAL

PTS Single Transfer Mode Control Block

In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).

Figure 5-12. PTS Control Block – Single Transfer Mode

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† In single transfer mode, the DU and SU bits and DI and SI bits are paired. Each pair must be set or cleared together. However, the two pairs, DU/SU and DI/SI, need not be equal.

Figure 5-12. PTS Control Block – Single Transfer Mode (Continued)

The PTSCB in Table 5-5 defines nine PTS cycles. Each cycle moves a single word from location 20H to an external memory location. The PTS transfers the first word to location 6000H. Then it increments and updates the destination address and decrements the PTSCOUNT register; it does not increment the source address. When the second cycle begins, the PTS moves a second word from location 20H to location 6002H. When PTSCOUNT equals zero, the PTS will have filled locations 6000H–600FH, and an end-of-PTS interrupt is ge nerated.

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