8XC196Kx, Jx, CA USER’S MANUAL

6.At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.

Notice that the “preamble” and exit code for this routine does not save or restore register RAM. The interrupt service routine is assumed to allocate its own private set of registers from the lower register file. The general-purpose register RAM in the lower register file makes this quite practical. In addition, the RAM in the upper register file is available via windowing (see “Windowing” on page 4-13).

5.5.3Determining the Source of an Interrupt

When the transition detector detects an interrupt, it sets the corresponding bit in the INT_PEND or INT_PEND1 register (Figures 5-7 and 5-8). This bit is set even if the individual interrupt is disabled (masked). The pending bit is cleared when the program vectors to the interrupt service routine. INT_PEND and INT_PEND1 can be read, to determine which interrupts are pending. They can also be modified (written), either to clear pending interrupts or to generate interrupts under software control. However, we recommend the use of the read-modify-write instructions, such as AND and OR, to modify these registers.

Other methods could result in a partial interrupt cycle. For example, an interrupt could occur during an instruction sequence that loads the contents of the interrupt pending register into a temporary register, modifies the contents of the temporary register, and then writes the contents of the temporary register back into the interrupt pending register. If the interrupt occurs during one of the last four states of the second instruction, it will not be acknowledged until after the completion of the third instruction. The third instruction overwrites the contents of the interrupt pending register, so the jump to the interrupt vector will not occur.

5.5.3.1Determining the Source of Multiplexed Interrupts

On the 87C196CA, the CAN-controller interrupts are multiplexed into the single CAN interrupt input (INT13). The interrupt service routine associated with INT13 must read the CAN interrupt pending register (CAN_INT, Figure 12-19 on page 12-32) to determine the source of the interrupt request.

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STANDARD AND PTS INTERRUPTS

The EPA4–9 and COMP0–1 e vent interrupts, the EPA0–9 overrun interrupts, and the timer 1 and timer 2 overflow/underflow interrupts are multiplexed into EPAx. The interrupt service routine associated with EPAx must read the EPA interrupt pending registers (EPA_PEND and EPA_PEND1) to determine the source of the interrupt request (see Figure 10-14 on page 10-28 and Figure 10-15 on page 10-29).

When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit.

† Bits 6–7 are reserved on the 87C196CA, 8XC196Jx devices. For compatibility with future devices, write zeros to these bits.

Figure 5-7. Interrupt Pending (INT_PEND) Register

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