8XC196Kx, Jx, CA USER’S MANUAL

4.1.6Internal RAM (Code RAM)

These devices have up to 512 bytes of internal RAM (see Table 4-1 on page 4-2 for details) beginning at location 0400H. Although it is sometimes called code RAM to distinguish it from register RAM, this internal RAM can store either executable code or data. The code RAM is accessed through the memory controller, so code executes as it would from external memory with zero wait states. Data stored in this area must be accessed with indirect or indexed addressing, so data accesses to this area take longer than data accesses to the register RAM. The code RAM cannot be windowed.

4.1.7Register File

The register file (Figure 4-1) is divided into an upper register file and a lower register file. The upper register file consists of general-purpose register RAM. The lower register file contains gen- eral-purpose register RAM along with the stack pointer (SP) and the CPU special-function registers (SFRs).

Table 4-1 on page 4-2 lists the register file memory addresses. The RALU accesses the lower register file directly, without the use of the memory controller. It also accesses a windowed location directly (see “Windowing” on page 4-13). The upper register file and the peripheral SFRs can be windowed. The 8XC196JV has additional register RAM in locations 1C00–1DFFH. Like the general-purpose register RAM in the upper register file, this register RAM can be windowed and is accessed directly, without the use of the memory controller. Registers in the lower register file and registers being windowed can be accessed with register-direct addressing.

NOTE

The register file must not contain code. An attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory.

4-10

MEMORY PARTITIONS

Address

03FFH (CA, JT, JV, KS, KT)

General-purpose

Register RAM

4-11

8XC196Kx, Jx, CA USER’S MANUAL

4.1.7.1General-purpose Register RAM

The lower register file contains general-purpose register RAM. The stack pointer locations can also be used as general-purpose register RAM when stack operations are not being performed. The RALU can access this memory directly, using register-direct addressing.

The upper register file also contains general-purpose register RAM. The RALU normally uses indirect or indexed addressing to access the RAM in the upper register file. Windowing enables the RALU to use register-direct addressing to access this memory. (See Chapter 3, “Programming ConsiderAtions,” for a discussion of addressing modes.) Windowing can provide for fast context switching of interrupt tasks and faster program execution. (See “Windowing” on page 4-13.) PTS control blocks and the stack are most efficient when located in the upper register file.

The 8XC196JV has additional register RAM in locations 1C00–1DFFH. Like the general-pur- pose register RAM in the upper register file, this register RAM can be windowed and is accessed directly, without the use of the memory controller.

4.1.7.2Stack Pointer (SP)

Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address of the stack. The SP must point to a word (even) address that is two bytes greater than the desired starting address. Before the CPU executes a subroutine call or interrupt service routine, it decrements the SP by two and copies (PUSHes) the address of the next instruction from the program counter onto the stack. It then loads the address of the subroutine or interrupt service routine into the program counter. When it executes the return-from-subroutine (RET) instruction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the contents of the top of the stack (that is, the return address) into the program counter and increments the SP by two.

Subroutines may be nested. That is, each subroutine may call other subroutines. The CPU PUSHes the contents of the program counter onto the stack each time it executes a subroutine call. The stack grows downward as entries are added. The only limit to the nesting depth is the amount of available memory. As the CPU returns from each nested subroutine, it POPs the address off the top of the stack, and the next return address moves to the top of the stack.

Your program must load a word-aligned (even) address into the stack pointer. Select an address that is two bytes greater than the desired starting address because the CPU automatically decrements the stack pointer before it pushes the first byte of the return address onto the stack. Remember that the stack grows downward, so allow sufficient room for the maximum number of stack entries. The stack must be located in either the internal register file or external RAM. The stack can be used most efficiently when it is located in the register file.

4-12