MEMORY PARTITIONS

8XC196Kx, Jx, CA USER’S MANUAL

NOTES:

1.The 8XC196JT, JV, and KS are offered in automotive temperature ranges only. The 8XC196CA, JQ, JR, KQ, KR, and KT are offered in both automotive and commercial temperature ranges.

2.After a reset, the device fetches its first instruction from 2080H.

3.The content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly.

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MEMORY PARTITIONS

4.1.3Program Memory

Program memory occupies a memory partition beginning at 2080H. (See Table 4-1 for the ending address for each device.) This entire partition is available for storing executable code and data. The EA# signal controls access to program memory. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low. For devices without internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.

NOTE

We recommend that you write FFH (the opcode for the RST instruction) to unused program memory locations. This causes a device reset if a program unintentionally begins to execute in unused memory.

4.1.4Special-purpose Memory

Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains several reserved memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transaction server (PTS) and standard interrupts. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low. For devices without internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.

Table 4-2. Special-purpose Memory Addresses

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8XC196Kx, Jx, CA USER’S MANUAL

4.1.4.1Reserved Memory Locations

Several memory locations are reserved for testing or for use in future products. Do not read or write these locations except to initialize them. The function or contents of these locations may change in future revisions; software that uses reserved locations may not function properly. Always initialize reserved locations to the values listed in Table 4-2 on page 4-3.

4.1.4.2Interrupt and PTS Vectors

The upper and lower interrupt vectors contain the addresses of the interrupt service routines. The peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks. See Chapter 5, “Standard and PTS Interrupts,” for more information on interrupt and PTS vectors.

4.1.4.3Security Key

The security key prevents unauthorized programming access to the nonvolatile memory. See Chapter 16, “Programm ing the Nonvolatile Memory,” for details.

4.1.4.4Chip Configuration Bytes (CCBs)

The chip configuration bytes (CCBs) specify the operating environment. They specify the bus width, bus-control mode, and wait states. They also control powerdown mode, the watchdog timer, and nonvolatile memory protection.

The CCBs are the first bytes fetched from memory when the device leaves the reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs). Once they are loaded, the CCRs cannot be changed until the next device reset. Typically, the CCBs are programmed once when the user program is compiled and are not redefined during normal operation. “Chip Configuration Registers and Chip Configuration Bytes” on page 15-4 describes the CCBs and CCRs.

For devices with user-programmable nonvolatile memory, the CCBs are loaded for normal operation, but the PCCBs are loaded into the CCRs if the device is entering programming modes. See Chapter 16, “Programm ing the Nonvolatile Memory,” for details.

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MEMORY PARTITIONS

4.1.5Special-function Registers (SFRs)

These devices have both memory-mapped SFRs and peripheral SFRs. The memory-mapped SFRs must be accessed using indirect or indexed addressing modes, and they cannot be windowed. The peripheral SFRs are physically located in the on-chip peripherals, and they can be windowed (see “Windowing” on page 4-13). Do not use reserved SFRs; write zeros to them or leave them in their default state. When read, reserved bits and reserved SFRs return undefined values.

NOTE

Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results. External events can change the contents of SFRs, and some SFRs are cleared when read. For this reason, consider the implications of using an SFR as an operand in a read-modify-write instruction (e.g., XORB).

4.1.5.1Memory-mapped SFRs

Locations 1FE0–1FFFH contain memory-mapped SFRs (see Table 4-3). Locations in this range that are omitted from the table are reserved. The memory-mapped SFRs must be accessed with indirect or indexed addressing modes, and they cannot be windowed. If you read a location in this range through a window, the SFR appears to contain FFH (all ones). If you write a location in this range through a window, the write operation has no effect on the SFR.

The memory-mapped SFRs are accessed through the memory controller, so instructions that operate on these SFRs execute as they would from external memory with zero wait states.

Table 4-3. Memory-mapped SFRs

Ports 3, 4, 5, Slave Port, UPROM SFRs

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