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8XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf
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8XC196Kx, Jx, CA USER’S MANUAL

Table 16-10. Timing Mnemonics (Continued)

Mnemonic

Description

 

 

TPHPL

PROG# High to Next PROG# Low.

TPHIL

PROG# High to AINC# Low.

TILIH

AINC# Pulse Width.

TILVH

PVER Hold After AINC# Low.

TILPL

AINC# Low to PROG# Low.

TPHVL

PROG# High to PVER Valid.

16.9 AUTO PROGRAMMING MODE

The auto programming mode is a low-cost programming alternative. Using this programming mode, the device programs itself with data from an external EPROM (external locations 4000H and above). A bank switching mechanism supplied by P1.2 and P1.1 supports auto programming of devices with more than 16 Kbytes of internal memory.

16.9.1 Auto Programming Circuit and Memory Map

Figure 16-12 shows the recommended circuit for an 8XC196Kx device and Table 16-11 shows the memory map for auto programming mode. Auto programming is specified for a crystal frequency of 6 to 8 MHz for commercial devices and 6 to 10 MHz for automotive devices. At 8 MHz, use a 27(C)512 EPROM with tACC = 250 ns and tOE = 100 ns or faster specifications. At 10 MHz, use a 27(C)512 EPROM with tACC = 245 ns and tOE = 100 ns or faster specifications.

Tie the BUSWIDTH pin low to configure an 8-bit data bus. Connect P1.1 and P1.2 as shown to generate the high-order bits of the external EPROM address. Connect P0.7:4 to VSS and VCC to select auto programming (1100B = 0CH). PACT# and PVER are status outputs, buffered by the 74HC14s. They drive LEDs that indicate programming active (PACT#) and programming verification (PVER). Connect all unused inputs to ground (VSS) and leave unused outputs floating. READY and NMI are active; connect them as indicated.

NOTE

All external EPROM addresses specified in this section are given for the circuit in Figure 16-12. If you choose a different circuit, you must adjust the addresses accordingly.

16-26

PROGRAMMING THE NONVOLATILE MEMORY

 

 

 

 

 

VCC

 

20 pF

 

 

 

20 pF

100 kΩ

 

 

XTAL1

 

XTAL2

 

 

 

 

 

 

 

 

VCC

RESET#

 

 

Reset

+5.0V

 

VCC

74HC14

1 kΩ

1.0µF

READY/P5.6

 

 

10µF

 

 

VSS

 

 

 

 

 

 

NMI

 

 

 

 

BUSWIDTH/P5.7

 

 

 

 

EA#

 

 

 

 

 

+12.50V

VPP

 

 

 

 

 

VCC

 

 

 

 

 

 

 

VREF

RD#/P5.3

 

 

 

 

P0.7/

 

 

 

 

 

 

PMODE.3

 

 

 

OE#

CE#

 

P0.6/

 

 

 

 

 

P1.2

 

A15

 

 

PMODE.2

 

 

 

 

P0.5/

 

P1.1

 

A14

 

 

 

 

 

 

 

 

PMODE.1

 

AD13:8

 

A13:8

 

 

P0.4/

 

 

 

VCC

 

 

 

 

 

PMODE.0

 

 

 

 

 

270kΩ

ANGND

 

 

 

 

 

 

ALE/P5.0

LE

OE#

 

 

 

 

 

 

27(C)512

 

P2.7/PACT#

AD7:0

 

A7:0

 

 

 

 

 

74LS373

O7:0

74HC14

 

 

 

 

 

ON = Programming

P2.5

 

 

 

 

 

 

 

 

 

 

P2.4

 

 

 

 

 

VCC

P2.3

 

 

 

 

 

P2.2

 

 

 

 

 

 

P2.1

 

 

 

 

 

270kΩ

 

 

 

 

 

 

 

P2.0/PVER

 

 

 

 

 

74HC14

87C196 Device

 

 

 

ON = Error

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0296-03

Figure 16-12. Auto Programming Circuit for 8XC196Kx Devices

NOTE

The 8XC196CA and Jx devices support only a 16-bit, zero-wait-state bus configuration for auto programming. For these devices, omit the BUSWIDTH, P2.5, and P2.3 connections (the pins are not implemented). For the 8XC196Jx, also omit the NMI connection (the pin is not implemented).

16-27

8XC196Kx, Jx, CA USER’S MANUAL

Table 16-11. Auto Programming Memory Map

Address

 

Address

 

Output from

Internal

Using Circuit

 

8XC196

OTPROM

in Figure

Description

Device

Address

16-12

 

(A15:0)

 

(P1.2:1, A13:0)

 

 

 

 

 

4014H

N/A

14H

Programming pulse width (PPW) LSB.

 

 

 

 

4015H

N/A

15H

Programming pulse width (PPW) MSB.

 

 

 

 

4020–402FH

2020–202FH

0020–002FH

Security key for verification.

 

 

 

 

4000–6FFFH

2000–4FFFH

4000–6FFFH

Code, data, and reserved locations. (KQ, JQ)

 

 

 

 

4000–7FFFH

2000–5FFFH

4000–7FFFH

Code, data, and reserved locations. (KR, JR)

 

 

 

 

4000–7FFFH

2000–7FFFH

4000–9FFFH

Code, data, and reserved locations. (KS)

 

 

 

 

4000–7FFFH

2000–9FFFH

4000–BFFFH

Code, data, and reserved locations. (KT, JT, CA)

 

 

 

 

A000–FFFEH

2000–7FFEH

2000–4FFFH

Code, data, and reserved locations. (JV)

8000–DFFEH

8000–DFFEH

5000–7FFFH

 

 

 

 

 

16.9.2 Operating Environment

In the auto programming mode, the PCCBs are loaded into the chip configuration registers. Since the device gets programming data through the external bus, the memory device in the programming system must correspond to the default configuration (Figure 16-6 on page 16-19). Auto programming requires an 8-bit bus configuration, so the circuit must tie the BUSWIDTH pin low. The PCCB defaults allow you to use any standard EPROM that satisfies the AC specifications listed in the device datasheet.

The auto programming mode also loads CCB0 into an internal RAM location and checks the lock bits. If either lock bit is programmed, the auto programming routine compares the internal security key to the external security key location. If the verification fails, the device enters an endless internal loop. If the security keys match, the routine continues. The auto programming routine uses the modified quick-pulse algorithm and the pulse width value programmed into the external EPROM (locations 14H and 15H).

16.9.3 Auto Programming Routine

Figure 16-13 illustrates the auto programming routine. This routine checks the security lock bits in CCB0; if either bit is programmed, it compares the internal security key to the external security key locations. If the security keys match, the routine continues; otherwise, the device enters an endless loop.

16-28

PROGRAMMING THE NONVOLATILE MEMORY

Other

No

PMODE = 0CH

Yes

 

 

 

 

Modes

 

 

 

 

 

 

 

?

 

 

 

 

 

 

 

 

 

 

 

 

 

 

No

Lock Bits

 

 

 

 

 

 

 

Enabled

 

 

 

 

 

 

 

?

 

 

 

 

 

 

 

Yes

 

 

 

 

 

 

 

Verify

 

 

 

 

 

 

 

Security Key

 

 

 

 

 

 

 

Pass

No

Loop

 

 

 

 

 

?

 

Forever

 

 

 

 

 

Yes

 

 

 

 

 

 

 

Load PPW

 

Assert PACT#

 

 

 

 

 

 

 

Get External Data

 

 

 

 

 

 

Yes

Data = 0FFFFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

?

 

 

 

 

 

 

 

No

 

 

 

 

 

 

 

Execute Modified

 

 

 

 

 

 

Quick-Pulse Algorithm

 

 

 

 

 

 

 

then Return

 

 

 

 

 

 

 

Error

No

 

 

 

 

 

 

Programming

 

 

 

 

 

 

 

 

 

 

 

 

 

?

 

 

 

 

 

 

 

Yes

 

 

 

 

 

 

 

Clear PVER

 

 

 

 

 

 

 

Increment Address Pointer

 

 

 

 

 

No

Top of

Yes

Deassert PACT#

 

 

 

 

Loop Forever

 

 

 

 

 

OTPROM

 

 

 

 

 

 

 

(Done)

 

 

 

 

 

?

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0191-03

Figure 16-13. Auto Programming Routine

16-29

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