8XC196Kx, Jx, CA USER’S MANUAL

XTAL1

1 State Time 1 State Time

PH1

PH2

CLKOUT

A0114-02

Figure 2-4. Internal Clock Phases

The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. The following formulas calculate the frequency of PH1 and PH2 and the duration of a state time (FOSC is the input frequency to the divide-by-two circuit).

Because the device can operate at many frequencies, this manual defines time requirements in terms of state times rather than specific times. Consult the latest datasheet for AC timing specifications.

Table 2-2. State Times at Various Frequencies

2.5INTERNAL PERIPHERALS

The internal peripheral modules provide special functions for a variety of applications. This section provides a brief description of each peripheral and other chapters describe each one in detail.

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ARCHITECTURAL OVERVIEW

2.5.1I/O Ports

The 8XC196Kx, 8XC196Jx, and 87C196CA have seven I/O ports, ports 0–6. Individual port pins are multiplexed to serve as standard I/O or to carry special-function signals associated with an on-chip peripheral or an off-chip component. If a particular special-function signal is not used in an application, the associated pin can be individually configured to serve as a standard I/O pin. Ports 3 and 4 are exceptions. Their pins must be configured either as all I/O or as all address/data.

Port 0 is an input-only port that is also the analog input for the A/D converter. Ports 1, 2, and 6 are standard, bidirectional I/O ports. Port 1 provides pins for the EPA and timers. Port 2 provides pins for the serial I/O (SIO) port, interrupts, bus control signals, and clock generator. Port 6 provides pins for the event processor array (EPA) and synchronous serial I/O (SSIO) port.

Ports 3, 4, and 5 are memory-mapped, bidirectional I/O ports. Ports 3 and 4 serve as the external address/data bus. Port 5 provides bus control signals; for the 8XC196Kx, it can also provide pins for the slave port. Chapter 6, “I/O Ports,” describes the I/O ports in more detail.

NOTE

The 87C196CA device does not implement the following port pins: P0.1:0, P1.7:4, P2.5 and P2.3, P5.7 and P5.1, and P6.3:2. See “Design Considerations for 87C196CA Devices” on page 2-13 for details.

The 8XC196Jx devices do not implement the following port pins: P0.1:0, P1.7:4, P2.5 and P2.3, P5.7:4, and P6.3:2. See “Design Considerations for 8XC196JQ, JR, JT, and JV Devices” on page 2-14 for details.

2.5.2Serial I/O (SIO) Port

The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchronous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous modes are full duplex, meaning that they can transmit and receive data simultaneously. The receiver is buffered, so the reception of a second byte may begin before the first byte is read. The transmitter is also buffered, allowing continuous transmissions. See Chapter 7, “Serial I/O (SIO) Port,” for details.

2.5.3Synchronous Serial I/O (SSIO) Port

The synchronous serial I/O (SSIO) port provides for simultaneous, bidirectional communications between two 8XC196 family devices or between an 8XC196 device and another synchronous serial I/O device. The SSIO port consists of two identical transceiver channels with a dedicated baud-rate generator. The channels can be programmed to operate in several modes. See Chapter 8, “Synchronous Serial I/O (SSIO) Port,” for more information.

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8XC196Kx, Jx, CA USER’S MANUAL

2.5.4Slave Port (8XC196Kx Only)

The slave port offers an alternative for communication between two CPU devices. Traditionally, system designers have had three alternatives for achieving this communication — a serial link, a parallel bus without a dual-port RAM (DPRAM), or a parallel bus with a DPRAM to hold shared data.

NOTE

The 87C196CA and 8XC196Jx devices do not implement the slave port chipselect and interrupt signals, so you cannot use the slave port on an 87C196CA or 8XC196Jx device.

A serial link, the most common method, has several advantages: it uses only two pins from each device, it needs no hardware protocol, and it allows for error detection before data is stored. However, it is relatively slow and involves software overhead to differentiate data, addresses, and commands. A parallel bus increases communication speed, but requires more pins and a rather involved hardware and software protocol. Using a DPRAM offers software flexibility between master and slave devices, but the hardware interconnect uses a demultiplexed bus, which requires even more pins than a simple parallel connection does. The DPRAM is also costly, and error detection can be difficult. The SSIO offers a simple means for implementing a serial link. The multiplexed address/data bus can be used to implement a parallel link, with or without a DPRAM. The slave port offers a fourth alternative.

The slave port offers the advantages of the traditional methods, without their drawbacks. It brings the DPRAM on-chip. With this configuration, an external processor (master) can simply read from and write to the on-chip memory of the 8XC196 (slave) device. The slave port requires more pins than a serial link does, but fewer than the number used for a parallel bus. It requires no hardware protocol, and it can interface with either a multiplexed or a demultiplexed bus. The master simply reads or writes as if there were a DPRAM device on the bus. Data error detection can be handled through the software. See Chapter 9, “Slave Port,” for details.

2.5.5Event Processor Array (EPA) and Timer/Counters

The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it. This is a capture event. In the output mode, the EPA monitors a timer until its value matches that of a stored time value. When a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin. This is a compare event. Both capture and compare events can initiate interrupts, which can be serviced by either the interrupt controller or the PTS.

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