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8XC196Kx,8XC196Jx,87C196CA microcontroller family user's manual.1995.pdf
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8XC196Kx, Jx, CA USER’S MANUAL

If you want to allow slave and auto programming as well as ROM dumps, leave both PCCB0 lock bits unprogrammed. To protect against unauthorized programming, clear the CCB0 lock bits and program an internal security key. After the device enters either slave or auto programming mode, the corresponding test ROM routine reads the CCB0 lock bits. If either CCB0 lock bit is enabled, the routine compares the internal security key location with an externally supplied security key. If the security keys match, the routine continues; otherwise, the device enters an endless internal loop.

You can program the internal security key in either auto or slave programming mode. Once the security key is programmed, you must provide a matching key to gain access to any programming mode. For auto programming and ROM-dump modes, a matching security key must reside in external memory. For slave programming mode, you must “program” a matching security key into the appropriate OTPROM locations with the program word command. The locations are not actually programmed, but the data is compared to the internal security key.

The serial programming mode checks the internal security key regardless of the CCB0 lock bits. This mode has no provision for security key verification. If the security key is blank (FFFFH), serial programming continues. If any word contains a value other than FFFFH, the device enters an endless internal loop.

WARNING

If you leave the internal security key locations unprogrammed (filled with FFFFH), an unauthorized person could gain access to the OTPROM by using an external EPROM with an unprogrammed external security key location or by using slave or serial port programming mode.

16.3.2 Controlling Fetches from External Memory

Two UPROM bits disable external instruction fetches and external data fetches. If you program the UPROM bits, an attempt to fetch data or instructions from external memory causes a device reset. Another bit enables circuitry that can detect an oscillator failure and cause a device reset. You can program the UPROM bits using slave programming mode.

Programming the DEI bit prevents the bus controller from executing external instruction fetches. An attempt to load the slave program counter with an external address causes the device to reset itself. Because the slave program counter can be as much as four bytes ahead of the CPU program counter, the bus controller might prevent code execution from the last four bytes of internal memory. The automatic reset also gives extra protection against runaway code.

Programming the DED bit prevents the bus controller from executing external data reads and writes. An attempt to access data through the bus controller causes the device to reset itself. Setting this bit disables ROM-dump mode.

16-6

PROGRAMMING THE NONVOLATILE MEMORY

To program these bits, write the correct value to the location shown in Table 16-5 on page 16-8 using slave programming mode. During normal operation, you can determine the values of these bits by reading the UPROM special-function register (Figure 16-1).

USFR

Address:

1FF6H

 

Reset State:

XXH

The unerasable PROM (USFR) register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator. These bits can be programmed, but cannot be erased.

WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot be returned to Intel for failure analysis.

7

 

 

 

 

 

 

 

 

 

0

 

 

DEI

DED

 

OFD

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit

 

 

 

Function

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:4

Reserved; always write as zeros.

 

 

 

 

 

 

 

 

 

 

 

3

DEI

Disable External Instruction Fetch

 

 

 

 

 

 

 

Setting this bit prevents the bus controller from executing external

 

 

 

instruction fetches. Any attempt to load an external address initiates a

 

 

 

reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

DED

Disable External Data Fetch

 

 

 

 

 

 

 

Setting this bit prevents the bus controller from executing external data

 

 

 

reads and writes. Any attempt to access data through the bus controller

 

 

 

initiates a reset.

 

 

 

 

 

 

 

 

 

 

 

 

1

Reserved; always write as zero.

 

 

 

 

 

 

 

 

 

 

 

 

0

OFD

Oscillator Fail Detect

 

 

 

 

 

 

 

 

Setting this bit enables the device to detect a failed oscillator and reset

 

 

 

itself. (In EPROM packages, this bit can be erased.)

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 16-1. Unerasable PROM (USFR) Register

You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this reason, Intel cannot test the bits before shipment. However, Intel does test the features that the UPROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells themselves.

16-7

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