15.8 SYSTEM BUS AC TIMING SPECIFICATIONS

A

RD#

B

WR#, WRH#, WRL#

BR

XTAL1

C

READY

D

Table 15-8. AC Timing Definitions

Symbol

Definition

The External Memory System Must Meet These Specifications

TAVDV

Address Valid to Input Data Valid

Maximum time the memory device has to output valid data after the 87C196CA, 8XC196Jx, Kx

outputs a valid address.

T

Address Valid to BUSWIDTH† Valid

AVGV

Maximum time after address is valid until BUSWIDTH must be valid. If this specification is

exceeded, the 8XC196Kx may not respond with the specified bus cycle.

T

Address Valid to READY†† Setup

AVYV

Maximum time the memory system has to assert READY after the 87C196CA, 8XC196Kx

outputs the address to guarantee that at least one wait state will occur.

TCLDV

CLKOUT Low to Input Data Valid

Maximum time the memory system has to output valid data after CLKOUT falls.

T

BUSWIDTH† Hold after CLKOUT Low

CLGX

Minimum time BUSWIDTH must be held valid after CLKOUT falls. Always 0 ns on the

8XC196Kx.

T

READY†† Hold after CLKOUT Low

CLYX

Minimum hold time is always 0 ns. If maximum specification is exceeded, additional wait states

will occur.

Table 15-8. AC Timing Definitions (Continued)

Symbol

Definition

The External Memory System Must Meet These Specifications (Continued)

ALE Low to BUSWIDTH† Valid

Maximum time after ALE/ADV# falls until BUSWIDTH must be valid. If this specification is

exceeded, the 8XC196Kx may not respond with the specified bus cycle.

TLLYH

ALE Low to READY†† Setup

Maximum time the memory system has to assert READY after ALE falls to guarantee that at

least one wait state will occur. (This specification is included only for comparison with HMOS

device timings.)

TLLYX

READY†† Hold after ALE Low

Minimum time the level of the READY signal must be valid after ALE falls. If the maximum

value is exceeded, additional wait states will occur.

TRHDX

Data Hold after RD# High

Time after RD# is inactive that the memory system must hold data on the bus. Always 0 ns.

TRHDZ

RD# High to Input Data Float

Time after RD# is inactive until the memory system must float the bus. If this timing is not met,

bus contention will occur.

TRLDV

RD# Low to Input Data Valid

Maximum time the memory system has to output valid data after the 87C196CA, 8XC196Jx,

Kx asserts RD#.

The 87C196CA, 8XC196Jx, Kx Meets These Specifications

FXTAL

Frequency on XTAL

Frequency of the signal input on the XTAL1 input. The internal bus speed of the 87C196CA,

8XC196Jx, Kx device is ½ F XTAL.

TOSC

1/FXTAL

All AC Timings are referenced to TOSC.

TAVLL

Address Setup to ALE/ADV# Low: Length of time address is valid before ALE/ADV# falls. Use

this specification when designing the external latch.

TCHCL

CLKOUT High Period

Needed in systems that use CLKOUT as clock for external devices.

TCHLH

CLKOUT High to ALE/ADV# High (8XC196KS, KT, modes 1 and 2 only)

Time between CLKOUT going high and ALE/ADV# going high. Use to derive other timings.

TCHWH

CLKOUT High to WR# High

Time between CLKOUT going high and WR# going inactive.

TCLCL

CLKOUT Cycle Time

Normally 2 TOSC.

TCLLH

CLKOUT Falling to ALE/ADV# Rising

Use to derive other timings.

Table 15-8. AC Timing Definitions (Continued)

Symbol

Definition

The 87C196CA, 8XC196Jx, Kx Meets These Specifications (Continued)

TWHAX

AD15:8 Hold after WR# High

Minimum time the high byte of the address in 8-bit mode will be valid after WR# inactive.

T

BHE#† , INST†† Hold after WR# High

WHBX

Minimum time these signals will be valid after WR# inactive. (8XC196Kx only)

TWHLH

WR# High to ALE/ADV# High

Time between WR# going inactive and next ALE/ADV#. Also used to calculate WR# inactive

and next address valid.

TWHQX

Data Hold after WR# High

Length of time after WR# rises that the data stays valid on the bus. Memory devices must meet

this specification.

TWLWH

WR# Low to WR# High

WR# pulse width.

TXHCH

XTAL1 High to CLKOUT High or Low