8XC196Kx, Jx, CA USER’S MANUAL

15.5.4 Regaining Bus Control (8XC196Kx Only)

While HOLD# is asserted, the device continues executing code until it needs to access the external bus. If executing from internal memory, it continues until it needs to perform an external memory cycle. If executing from external memory, it continues executing until the queue is empty or until it needs to perform an external data cycle. As soon as it needs to access the external bus, the device asserts BREQ# and waits for the external device to deassert HOLD#. After asserting BREQ#, the device cannot respond to any interrupt requests, including NMI, until the external device deasserts HOLD#. One state time after HOLD# goes high, the device deasserts HLDA# and, with no delay, resumes control of the bus.

If the device is reset while in hold, bus contention can occur. For example, a CPU-only device would try to fetch the chip configuration byte from external memory after RESET# was brought high. Bus contention would occur because both the external device and the device would attempt to access memory. One solution is to use the RESET# signal as the system reset; then all bus masters (including the device) are reset at once. Chapter 13, “Minimum Hardware Considerations,” shows system reset circuit examples.

15.6 BUS-CONTROL MODES

The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated during external read and write cycles. Table 15-5 lists the four bus-control modes and shows the CCR0.3 and CCR0.2 settings for each.

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Table 15-5. Bus-control Mode

† The BHE# and WRH# pins are not implemented on the 87C196CA, 8XC196Jx devices.

15.6.1 Standard Bus-control Mode

In the standard bus-control mode, the device generates the standard bus-control signals: ALE, RD#, WR#, and BHE# (see Figure 15-9). ALE is asserted while the address is driven, and it can be used to latch the address externally. RD# is asserted for every external memory read, and WR# is asserted for every external memory write. When asserted, BHE# selects the bank of memory that is addressed by the high byte of the data bus.

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Figure 15-9. Standard Bus Control

When the device is configured to use a 16-bit bus, separate lowand high-byte write signals must be generated for single-byte writes. Figure 15-10 shows a sample circuit that combines BHE# and AD0 to produce these signals (WRL# and WRH#). A similar pair of signals for read is unnecessary. For a single-byte read with the 16-bit bus, both bytes are placed on the data bus and the processor discards the unwanted byte.

BHE#

WRH#

WR#

WRL#

AD0

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Figure 15-10. Decoding WRL# and WRH#

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8XC196Kx, Jx, CA USER’S MANUAL

Figure 15-11 shows an 8-bit system with both flash and RAM. The flash is the lower half of memory, and the RAM is the upper half. This system configuration uses the most-significant address bit (AD15) as the chip-select signal and ALE as the address-latch signal.

Figure 15-11. 8-bit System with Flash and RAM

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Figure 15-12 shows a system that uses the dynamic bus-width feature. (The CCR bits, BW0 and BW1, are set.) Code is executed from the two EPROMs and data is stored in the byte-wide RAM. The RAM is in high memory. It is selected by driving AD15 high, which also selects the 8-bit bus width mode by driving the BUSWIDTH signal low.

Figure 15-12. 16-bit System with Dynamic Bus Width

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