Broadband Packet Switching Technologies

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Fig. 10.10 Example of desynchronization effect in CRRD Žn s m s k s 2..

How the pointers are desynchronized is demonstrated by using a simple example. Let us consider n s m s k s 2 as shown in Figure 10.10. We assume that every VOQ is always occupied with cells. Each VOQ sends a request to be selected as a candidate at every time slot. All the pointers are set to be PV Ži, ®. s 0, PLŽi, r . s 0, and PcŽr, j. s 0 at the initial state. Only one iteration in phase 1 is considered here.

At time slot T s 0, since all the pointers are set to 0, only one VOQ in

VOQŽ0, 1, 0., and VOQŽ1, 0, 0., can send cells. The related pointers with the grants are updated. Four VOQs can send cells at T s 2. In this situation, 100% switch throughput is achieved. There is no contention at the CMs from T s 2, because the pointers are desynchronized.

10.5THE PATH SWITCH

If we consider each input module and each output module as a node, a particular connection pattern in the middle stage of the Clos network can be

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consideration at all. We conceived the idea of quasistatic routing, called path switching, using a finite number of different connection patterns in the middle stage repeatedly, as a compromise of the above two extreme schemes.

For any given i j, if Ýi i j n F m, and Ýj i j n F m, we can always find a finite number f of regular bipartite multigraphs such that

f

Ý ei j Ž t .

where ei jŽt. is the number of edges from node i to node j in the t th bipartite multigraph. The capacity requirement Ž10.4. can be satisfied if the system provides connections repeatedly according to the coloring of these f bipartite multigraphs, and that finite amount of routing information can be stored in the local memory of each input module to avoid the slot-by-slot computation of route assignments. The path switching becomes circuit switching if f s 1, and it is equivalent to cell switching if f ™ .

The scheduling of path switching consists of two steps, the capacity assignment and the route assignment. The capacity assignment is to find the capacity Ci j i j for each virtual path between input module Ii and output module Oj; it can be carried out by optimizing some objective function subject to Ýi Ci j s Ýj Ci j s m. The choice of the objective function depends on the stochastic characteristic of the traffic on virtual paths and the quality of services requirements of connections.

The next step is to convert the capacity matrix wCi j x into edge coloring of a finite number f of regular bipartite multigraphs, each of which represents a particular connection pattern of central modules in the Clos network. An edge coloring of a bipartite multigraph is an assignment of m distinct colors to m edges of each node such that no two adjacent edges have the same color. It is well known that a regular bipartite multigraph with degree m is m-colorable w9, 15x. Each color corresponds to a central module, and the color assigned to an edge from input module i to output module j represents a connection between them through the corresponding central module.

Suppose that we choose a sufficiently large integer f such that fCi j are integers for all i, j, and form a regular bipartite multigraph, called the capacity graph, in which the number of edges between node i and node j is fCi j. Since the capacity graph is regular with degree fm, it can be edge-col- ored by fm different colors w15x. Furthermore, it is easy to show that any edge coloring of the capacity graph with degree fm is the superposition of the edge colorings of f regular bipartite multigraphs of degree m. Consider a

Fig. 10.12 Illustration of time space interleaving principle. Ž 1997 IEEE..

where r g 0, 1, . . . , m y 14 and t g 0, 1, . . . , f y 14 are the quotient and the remainder on dividing a by f, respectively. The mapping gŽa. s Žt, r . from the set 0, 1, . . . , fm y 14 ™ 0, 1, . . . , f y 14 0, 1, . . . , m y 14 is one-to- one and onto, that is,

a s a •´ t s t and r s r .

That is, the color assignment a, or equivalently the assignment pair Žt, r ., of the edge between Ii and Oj indicates that the central module r has been

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assigned to a route from Ii to Oj in the t th time slot of every cycle. Adopting the convention in TDMA system, each cycle will be called a frame, and the period f the frame size. As illustrated by the example shown in Figure 10.12, where m s 3 and f s 2, the decomposition of the edge coloring into assignment pairs guarantees that route assignments are either space-interleaved or time-interleaved. Thus, the relation Ž10.7. will be called the time space interlea®ing principle.

10.5.1Homogeneous Capacity and Route Assignment

For uniform traffic, where the distribution of traffic loading between input modules and output modules is homogeneous, the fm edges of each node can be evenly divided into k groups, where k is the total number of input or output modules. Each group contains g s fmrk edges between any input output pair, where the frame size f should be chosen to make the group size g an integer. The edges of this capacity graph can be easily colored by the Latin square given in Table 10.1, where each Ai , 0 F i F k y 1, represents a set of distinct colors, e.g.,

A0 s 0, 1, . . . , g y 14 , A1 s g , g q 1, . . . , 2 g y 14 , . . .

Aky1 s Ž k y 1. g , Ž k y 1. g q 1, . . . , kg y 14

Since each number in the set 0, 1, . . . , fm y 14 appears only once in any row or column in the table, it is a legitimate edge coloring of the capacity graph. The assignment a s Žt, r . of an edge between the Ii Oj pair indicates that the central module r will connect input module i to output module j in the t th slot of every frame. As an example, for m s 3 and k s 2, we can choose

Table 10.2, and the correspondence between the route assignments and the connection patterns in the middle stage is shown in Figure 10.13.

In the above example, since the number of central modules Žm. is greater than the number of input modules Žk., it is possible that more than one central module is assigned to some input output pair in one time slot. In the case that m k, there are not enough central modules for all input output

TABLE 10.1 Latin Square Assignment

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Fig. 10.14 Route scheduling in central modules for the second example of uniform traffic. Ž 1997 IEEE..

pairs in one time slot assignment. Nevertheless, the total number of central modules assigned to every input output pair within a frame should be the same for uniform input traffic to fulfill the capacity requirement, and that number is equal to g s fmrk. This point is illustrated in the following example. For m s 4 and k s 6, we choose f s 3 and g s 2. The same method will result in the connection patterns shown in Figure 10.14. It is easy to verify that the number of central modules Žpaths, edges. assigned for each input output pair is equal to g s 2 per f s 3 slots.

10.5.2Heterogeneous Capacity Assignment

The capacity assignment in a cross-path switch is virtual-path-based. It depends on the traffic load on each virtual path to allocate the capacity and determine the route assignment. The Latin square offers a legitimate capacity assignment with homogeneous traffic, but it may no longer be effective with heterogeneous traffic Žnonuniformly distributed traffic load over the virtual paths.. A more general assignment method is therefore introduced, and the procedure is illustrated in Figure 10.15. The assignment procedure has four steps, each of which will be explained along with an example in the following sub-subsections.

10.5.2.1 Virtual Path Capacity Allocation (VPCA) This step is to allocate capacity to each virtual path based on the traffic loads. It can be formulated as an optimization problem with some traffic modeling.

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The roundoff error is inversely proportional to f. Thus, the error can be arbitrary small if the frame size is sufficiently large. However, since the amount of routing information stored in the memory is linearly proportional to f, the frame size is limited by the access speed and the memory space of input modules. In practice, the choice of frame size f is a compromise between the roundoff error and the memory requirement. In general,

ji

In the above matrix E, each element ei j represents the number of the edges between the input module i and output module j in the k k capacity graph, in which each node has degree fm.

10.5.2.3 Edge Coloring As mentioned previously, this capacity graph can be colored by fm colors, and each color represents one distinct time space slot based on the time space interleaving principle Ž10.7.. Coloring can be found by complete matching, which is repeated recursively to reduce the degree of every node one by one. One general method to search for a complete matching is the so-called Hungarian algorithm or alternating-path

Fig. 10.16 Route scheduling example Žheterogeneous traffic.. Ž 1997 IEEE..

REFERENCES 277

and k is a power of two, an efficient parallel algorithm proposed in w7x for conflict-free route scheduling in a three-stage Clos network with time complexity of OŽlog2 Ž fmk.. can be used. Through the time space interleaving, the middle-stage routing pattern in Figure 10.16 is obtained.

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