Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)

pling rate of the on-chip D/A converter to have a variable non-integer relationship with the input symbol rates [Eru93]. This block is needed, because the specified D/A converter sampling rates and input symbol rates shown in Table 16-1 do not have an integer frequency relationship. The coordinate rotation digital computer (CORDIC) rotator translates the baseband-centered spectrum to a programmable carrier center frequency [Vol59]. The IF signal is filtered by an x/sinx filter for compensating the sample and hold response of the on-chip 14 bit D/A converter [Sam88]. The internal wordlengths of the modulator are shown in Figure 16-6. The wordlengths were chosen so that the 14-bit D/A converter quantization noise dominates the digital output noise.

16.3 Pulse Shaping and Half-band Filters

The input symbols are filtered using Gaussian (BT = 0.3)/linearized Gaussian/square root raised cosine (α = 0.22) pulse shaping filter in GSM/EDGE/WCDMA mode, respectively [GSM99a], [FDD00]. The square root raised cosine filter (excess bandwidth ratio = 0.22) was designed to maximize the ratio of the main channel power to the adjacent channels’ power under the constraint that the error vector magnitude (EVM) is below 2 % (-34 dB) (see section 0) [Van00]. In the GSM/EDGE systems, a quarter of a guard bit is inserted after each burst, resulting in a burst length of 156.25 symbols [GSM99b]. Therefore, the input symbols to the pulse shaping filter

18

out

Figure 16-7. Re-sampler.

have to be oversampled by 4 in the GSM and EDGE modes. The pulse shaping filter is implemented using programmable canonic signed digit (CSD) coefficients [Hau93].

The pulse shaping and the half-band filters are implemented using a polyphase structure (see section 11.8) [Fli94]. Taking advantage of the fact that in the modulator data streams in the I and Q paths are processed with the same functional blocks, a further hardware reduction can be achieved by pipeline interleaving techniques (see section 11.11) [Par99]. The pulse shaping and the half-band filters are modified to handle two channels by doubling the sampling rate and delay elements between taps. This results in a more efficient layout with a penalty in terms of increased power dissipation. The fixed coefficients of the half-band filters are implemented using CSD numbers (see section 11.6) [Sam89].

16.4 Re-Sampler

The re-sampler consists of a re-sampling NCO and a cubic Lagrange polynomial interpolator, as shown in Figure 16-7. The re-sampling NCO supplies sampling clocks for re-sampler (clk1), half-band and pulse shaping filters (clk1, clk1/2, clk1/4) as well as the trigger signal for the input data symbols (clk1/8). The frequency control word (∆φ) is calculated from the ratio of the input sampling rate of the re-sampler (clk1) to output sampling rate (clk).

Digital Sinusoidal Oscillator 2

27

-1 z-1

27

Figure 16-8. Ramp generator and output power level controller.

The trigger signals for different input symbol rates could be achieved by altering the frequency control word. The output of the re-sampling NCO ( k) may be considered to represent the phase offset between the input sampling rate of the re-sampler (clk1) to the output sampling rate (clk). Since the phase offset changes on every output sample clock cycle, the interpolation filter coefficients are time-varying. The time-varying filter coefficients with a long period can be easily implemented by polynomial-based interpolation filters using the so called a Farrow structure [Far98]. The cubic Lagrange polynomial interpolator was found suitable for our application because it fulfills spectral and time domain (phase error and EVM) specifications [GSM99c], [TDD00], [FDD00]. The cubic Lagrange polynomial interpolator is implemented with the Farrow structure [Eru93], where the number of unit delay elements is minimized as in Figure 16-7. Furthermore, the frequency error term generated by the external digital phase locked loop (DPLL) locking to an external symbol rate could be added to the frequency control word (∆φ) (see section 12.5.1) [Ket03].

16.5 CORDIC Rotator

The in-phase output of the CORDIC rotator is

where I(n), Q(n) are pulse shaped and interpolated quadrature data symbols. The carrier frequency is

Figure 16-9. Parallel Structure.

The constant A3 is 0.42A. The initial values of the rising Blackman ramp for the first oscillator are the negatives of the falling ramp values. In the case of the Hanning window, the initial values are the same as in the Blackman case for the first oscillator, the values for the second oscillator are zero and the constant A3 is 0.5A. The ramp duration (Tr) can be altered by changing the output frequencies of the digital oscillators. The value (A) controls the amplitude of the ramp (output power level). During the ramp period the signal sel is low in Figure 16-8 and the multiplexer conducts the ramp signal to the multiplier (Figure 16-6). After the ramp duration (Tr) the signal sel becomes high; the output of the multiplexer is connected to the input of the multiplexer; and the output power level is constant.

16.6.3 Parallel Structure

The recursive digital oscillator shown in Figure 16-8 suffers from two major drawbacks: the quantization noise accumulates in the recursive structure and the maximum sampling rate of the digital oscillator is determined by its recursive parts. The oscillator produces only one cycle of sine wave in the

(b)

Figure 16-10. Multicarrier options: a) Parallel upconverters. b) Synthesis filter bank based.

can also be improved by making fine frequency adjustments in the complex baseband [Paš01]. The fine carrier frequency resolution could be achieved with low hardware cost, as in Figure 16-10(a), by programming the QDDS [Van01]. The fine carrier frequency resolution gives a high degree of flexibility in IF and RF frequency planning. The choice was therefore made in favor of the parallel upconverter architecture (combining a number of parallel modulator outputs in Figure 16-6).

16.8 Design Flow

This chapter gives a brief overview of the design flow and the software used when the GSM/EDGE/WCDMA modulator circuit was implemented. A simplified diagram of the design flow is shown in Figure 16-11. Of course, some of the stages in the design flow were performed simultaneously supporting one another.

System specifications

Figure 16-11. Design flow.

16.8.1 High Level Modeling

After and during the system specifications made in collaboration with Nokia Networks, high level modeling and simulation were performed. A simulation model with a graphical user interface was developed using the Matlab signal processing tool. The purpose of this model was mainly to model the effects of the finite precision in the digital circuit and the nonidealities of the D/A- converter on the precision of modulation and signal spectrum.

16.8.2 Hardware Description

After the high level modeling, the Register Transfer Level (RTL) description was written in VLSI Hardware Description Language (VHDL). Keeping in mind the future work, the VHDL descriptions were made modular and parameterizable. The test benches and the simulation scripts were developed to ease the simulations. The VHDL code was simulated using Modelsim and the results were viewed and verified using Matlab.

16.8.3 Logic Synthesis

When the performance of the VHDL description was found appropriate, the VHDL description was read into the Synopsys Design Compiler for logic synthesis. First, the timing information was provided from the technology

Current Output

Figure 16-12 Block diagram of the 14-b D/A converter

libraries. The VHDL description was synthesized to the logic elements meeting the given timing constraints. In some resource demanding blocks, for example, in re-samplers, an automatic pipelining feature of the Synopsys Behavioral Compiler was used [Syn99]. A top-down hierarchal compilation strategy described in [Bha99] with some modifications was used to compile the main blocks of the design. Thereafter, the design was grouped together and flattened. The static timing analysis was performed using the Design Compiler and the functionality of the synthesized design was verified by Formality and Modelsim.

16.8.4 Layout Synthesis

A floorplan with a so-called black-box reserving the area for the D/A- converter was generated in the Cadence Envisia Design Planner. The synthesized VERILOG netlist and the floorplan of the design were transferred to the Cadence Envisia Silicon Ensemble layout synthesis tool. In order to enable the timing driven place and route, the timing constraints were also provided for these tools. After the power planning and the initial placement of cells were performed, the clock tree was generated and the placement was optimized using the stand-alone programs CTGEN and PBOPT, respectively. Thereafter, the layout was routed. Exploiting the timing information available after the routing, another placement optimization was performed, followed by a new round of routing.

The timing and the functionality of the completed layout of the digital part was verified using Design Compiler and Modelsim, respectively.

16.8.5 Final Layout

After the digital part of the modulator was designed and verified, the layout was transferred into Mentor IC-station for the final manual editing. The ana-

Figure 16-13. Block diagram of test system.