Vankka J. - Digital Synthesizers and Transmitters for Software Radio (2000)(en)

The noise coupling and clock jitter might be a problem in a programmable logic device (PLD), so an off-chip 1 bit D/A converter was used. In the fully differential system used here, the D/A converter output rise and fall are inherently symmetric, so that a simple non-return-to-zero output suffices [Jen95]. The one bit D/A converter is a simple current-steering differential pair with a current source.

14.6 Implementations

The DDS with tunable ∆¦ modulator (real and complex) were implemented with the Altera FLEX 10KA-1 series devices [Fle98]. The DDS (in Figure 14-1) with the tunable real ∆¦ modulator requires 1089 (21 % of the total) logic elements (LEs) in the EPF10K100A device. The DDS (in Figure 14-2) with the tunable complex ∆¦ modulator requires 2098 (42% of the total) LEs in the EPF10K100A device. The maximum operating frequency of the real and complex realization is 30 and 40 MHz, respectively. The most significant bit of the 14-bit D/A converter was used as a 1 bit D/A converter [Kos01].

14.7 Measurement Results

To evaluate the DDS with tunable ∆¦ modulator (real and complex) a test

-10

-30

1AVG

-50

-60

-70

-80

-110

Figure 14-9. Spectrum of 20 MHz signal at 1-bit ∆¦ D/A converter output, where sampling frequency is 40 MHz.

[Jan97] S. A. Jantzi, K. W. Martin, and A. S. Sedra, "Quadrature Bandpass ¦∆ Modulation for Digital Radio," IEEE J. of Solid State Circuits, Vol. 32, No. 12, pp. 1935-1950, Dec. 1997.

[Jay98] A. Jayaraman, P. F. Chen, G. Hanington, L. Larson, and P. Asbeck, "Linear High-Efficiency Microwave Power Amplifiers Using Bandpass Delta-Sigma Modulators," IEEE Microwave and Guided Wave Letters, Vol. 8, No. 3, pp. 121 –123, March 1998.

[Jen95] J. F. Jensen, G. Raghavan, A. E. Cosand, and R. H. Walden, "A 3.2- GHz Second-Order Delta-Sigma Modulator Implemented in InP HBT Technology," IEEE J. of Solid State Circuits, Vol. 30, No. 10, pp. 1119-1127, Oct. 1995.

[Key01] J. Keyzer, J. Hinrichs, A. Metzger, M. Iwamoto, I. Galton, and P. Asbeck, "Digital Generation of RF Signals for Wireless Communications with Band-Pass Delta-Sigma Modulation," IEEE Microwave Symposium Digest, Vol. 3, pp. 2127-2130, 2001.

[Kos01]M. Kosunen, J. Vankka, M. Waltari, and K. Halonen, "A Multicarrier QAM Modulator for WCDMA Base Station with on-chip D/A converter," In Proc. 2001 IEEE Custom Integrated Circuits Conference, May

2001, pp. 301-304.

[Mag97] A. J. Magrath, and M. B. Sandler, "Digital Power Amplification Using Sigma-Delta Modulation and Bit Flipping," J. Audio Eng. Soc., Vol. 45, No. 6, pp. 476-487, June 1997.

[McC84] R. D. McCallister, and D. Shearer, III, "Numerically Controlled Oscillator Using Quadrant Replication and Function Decomposition," U. S. Patent 4,486,846, Dec. 4, 1984.

[Nic91] H. T. Nicholas, and H. Samueli, "A 150-MHz Direct Digital Frequency Synthesiser in 1.25- m CMOS with -90-dBc Spurious Performance," IEEE J. Solid-State Circuits, Vol. 26, pp. 1959-1969, Dec. 1991.

[Nor97]S. R. Norsworthy, R. Schreier, and G. C. Temes, "Delta-sigma Data Converters, Theory, Design, and Simulation," New York: IEEE Press, 1997. [Sch03] W. Schofield, D. Mercer, and L. St. Onge, "A 16b 400MS/s DAC with <-80dBc IMD to 300 MHz and <-160dBm/Hz Noise Power Spectral Density," ISSCC Digest of Technical Papers, February 2003, San Francisco, USA, pp. 126-127.

[Tan95] L. K. Tan, and H. Samueli, "A 200 MHz Quadrature Digital Synthesizer/Mixer in 0.8 m CMOS," IEEE J. of Solid State Circuits, Vol. 30, No. 3, pp. 193-200, Mar. 1995.

[Van01] J. Vankka, and K. Halonen, "Direct Digital Synthesizers: Theory, Design and Applications," Kluwer Academic Publishers, 2001.

[Van98] J. Vankka, M. Waltari, M. Kosunen, and K. Halonen, "Direct Digital Syntesizer with on-Chip D/A-converter," IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp. 218-227, Feb. 1998.

Figure 15- 1 . The digital quadrature modulator replacing the first analog IF mixer stage.

15.1 Multiplier Free Quadrature Modulation

The output of the complex modulator in Figure 15-2 is

where Ii(n) and Qi(n) are pulse shaped and interpolated in-phase and quadra- ture-phase data symbols, which are upconverted to the orthogonal (in-phase (Xi(n)) and quadrature-phase (Yi(n))) carriers at frequency fCi [Van02], [Kos01]. The output of the quadrature modulator in Figure 15-2 is

where f and f ut are the sampling and output frequency, and X(n), Y(n) are interpolated in-phase and quadrature-phase carriers, respectively. Furthermore, if we require either the sine or cosine term to be zero in (15.2) at every n, then for each output value only one of the in-phase or quadrature-phase part needs be processed, which reduces the amount of hardware needed [Won91], [Dar70]. Solutions for f ut/f equal to 0, 1/2, 1/4, -1/4 in Table 4-2

correspond to our requirements. Using these values, high-speed digital multipliers and adders are not needed in the implementation of the quadrature

Figure 15-2 . Two complex modulators in series with the quadrature modulator.

the images are suppressed more in the lowpass mode, thus reducing the complexity of the analog reconstruction filter. Furthermore, the sin(x)/x rolloff over the effective passband is significantly reduced. In the lowpass/highpass mode, the information in the quadrature-phase carrier is lost, because output consists only of in-phase carriers in those modes (Table 4-2). The output frequency of the complex modulator (fCi) should be higher than

dc in those modes, because then the quadrature-phase data Qi(n) is modulated to the in-phase carrier in (15.1). Furthermore, the frequency should be considerably higher than dc in the lowpass/highpass mode, so that the images generated by the analog upconversion could be filtered by the bandpass filter (BPF 2 in Figure 15-1) (lowpass mode), and the images generated by the D/A conversion could be filtered by the analog reconstruction filter (BPF 1 in Figure 15-1) (highpass mode). In the bandpass mode there are no such restrictions.

The quadrature modulation in (15.2) is performed by the negators and 4:1 MUX shown in Figure 15-3. This may be considered to represent a frequency up-shift of the low-pass passband of the interpolation filters to the desired frequency. The digital modulator magnitude responses in the lowpass, bandpass and highpass modes are shown in Figure 15-4. The combination of the filters provides more than 74dB image rejection (passband ripple of 0.004dB). The transition band in the lowpass mode (Figure 15-4) is from 0.023 - 0.04 f. The images related to the last interpolation stage are shown in Figure 15-5. The image selection is achieved by changing the filter passband.

0

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-100

Figure 15-4. Digital quadrature modulator magnitude response in the lowpass (-), bandpass (--) and highpass mode ( ) in Figure 15-3.

In the bandpass mode, the first or second image in Figure 15-5 can be chosen by the negation of Y branches (control signals CTR4 and CTR5 in Figure 15-3). This selection can be made independently from each orthogonal carrier, thus almost doubling the output bandwidth in the bandpass mode, as shown in Figure 15-5. If the odd image is used, then the output spectrum might be inverted (mirrored about carrier frequency) in the complex modulator [Van02]. This is achieved by changing the sign of the complex modulator carrier frequency (the direction of the vector rotation) in (15.1).

The internal wordlengths of the modulator are shown in Figure 15-3. The wordlengths were chosen such that the 12-bit D/A converter quantization noise dominates the digital output noise.

15.3 D/A Converter

From a systems perspective, integration of the D/A converter into the digital system is desirable to avoid high-speed multi-bit data crossing over the interchip boundary. The 12-bit on-chip D/A converter is based on a segmented current steering architecture. It consists of a 6b MSB matrix (2b binary and 4b thermometer coded) and a 6b binary coded LSB matrix, as shown in Figure 15-6. The dynamic linearity is important in this modulator because of the strongly varying signal, although the good static linearity is a prerequisite for obtaining a good dynamic linearity. For a current-steering D/A converter, the static linearity is mainly determined by the matching behavior of the current sources and the finite output impedance of the current source. The static linearity is achieved by sizing the current sources for intrinsic matching, using layout techniques and increasing current cell output impedance by biasing the switch transistors in the saturation region and adding cascode devices.

Figure 15-5. Images in frequency domain.

The integral non-linearity (INL) of a D/A converter is in this book defined to be the difference between the analog output value and the straight line drawn between the output values corresponding to the smallest and the largest input code, divided by the average LSB step. The INL yield is then given by the ratio of the number of functional D/A converters ( INL < ±1/2 LSB) to the total number of try-outs. At the segmentation level of (4-8), the D/A converter suffers more severely from INL than differential non-linearity (DNL) according to the simulations, therefore the INL yield defines the requirements for standard deviation. In this case, for an INL yield of 99.99 %, a unit current source standard deviation of 0.26 % is required (Figure 10-3).

To minimize these three effects, a well designed and carefully laid out synchronized switch driver is used [Bos01]. A major function of the switch driver shown in Figure 15-7 is to adjust the crosspoint of the control voltages, and to limit their amplitude at the gates of the current switches, in such a way that these transistors are never simultaneously in the off state and that the feedthrough is minimized. The crossing point of the control signals is set by using different rise and fall times for the differential output of the driver [Bos01], [Wu95]. A buffer is inserted between the latch and the current cell to adjust further the crossing point of the differential outputs. The reduced voltage swing is achieved by lowering the power supply of the buffer. Dummy switch transistors were used to improve the synchronization of the switch transistors control signals. The sizing of the dummy transistors was optimized by simulations. The cascode transistor between the current sources and the switches is used to increase the output impedance of the current cell, which improves the linearity of the D/A-converter shown in Figure 15-7 [Tak91]. To minimize the feedthrough to the output lines and to increase the output impedance further in the current cell, the drain of the switching tran-

Current Output

Figure 15-6 Block diagram of the 12-b D/A converter.

sistors is isolated from the output lines by adding cascode transistors [Tak91]. Unfortunately, this cascode increases the output settling time and causes different rise and fall times for single-ended outputs, although the latter is cancelled partly in the differential output.

By dividing the current source array into separately biased MSBand LSB-arrays in such way that they both contain current sources for half the bits and that the MSB unit current source is 64 times wider than the LSB unit source, the number of unit current sources required falls from 1024 to 63+63 in a 12 bit D/A converter [Bas98]. This layout reduces the parasitic capacitances at the drain node of the current source transistors by reducing the amount of wiring needed to connect the transistors, as well as by reducing the parasitic capacitances caused by the transistors themselves [Bas98]. This improves the settling time of the converter [Chi94] and the output impedance at the higher signal frequencies [Bas98]. The scheme also reduces the area required by the current source matrices by allowing routing on top of the MSB transistors, as well as by reducing the amount of silicon area wasted in the process dependent spaces between the transistors [Bas98]. On the downside, the current generated by the MSB unit current sources has to be a very accurate 64 times the LSB unit current. This requires a trimmable biasing scheme for the MSB current sources.

15.4 Implementation and Layout

The digital part of the quadrature modulator, excluding the 4:1 MUX illustrated in Figure 15-3, was synthesized from the VHDL description using the standard 0.35 m CMOS cell library. Multirate systems are efficiently implemented using the polyphase structure in which sampling rate conversion and filtering operations are combined (see section 11.8). The problem is that, for the series of polyphase filters in Figure 15-3, there is much more computation during some of the sampling instants than others. Thus, the switching noise is periodic; this tends to affect the timing on the D/A converter current

Figure 15-7 Switch driver and current cell.