EXERCISES 237
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Figure 9.28 Block diagram of the system with PID controller
9.2.3.2 Closed-Loop Tuning
The Ziegler–Nichols closed-loop tuning algorithm is based on plant closed-loop tests. The procedure is as follows:
Disable any derivative and integral action in the controller and leave only the proportional action.
Carry out a set-point step test and observe the system response.
Repeat the set-point test with increased (or decreased) controller gain until a stable oscillation is achieved (see Figure 9.29). This gain is called the ultimate gain, Ku .
Read the period of the steady oscillation and let this be Pu .
Calculate the controller parameters according to the following formulae: K p = 0.45Ku , Ti = Pu /1.2 in the case of the PI controller; and K p = 0.6Ku , Ti = Pu /2, Td = Tu /8 in the case of the PID controller.
9.3 EXERCISES
1. The open-loop transfer function of a plant is given by:
e−4s
G(s) = .
1 + 2s
(a)Design a dead-beat digital controller for the system. Assume that T = 1 s.
(b)Draw the block diagram of the system together with the controller.
(c)Plot the time response of the system.
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Figure 9.29 Ziegler–Nichols closed-loop test
238 DISCRETE CONTROLLER DESIGN
2.Repeat Exercise 1 for a Dahlin controller. Plot the response and compare with the results obtained from the dead-beat controller.
3.The open-loop transfer function of a system together with a zero-order hold is given by
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Design a digital controller so that the closed-loop system will have ζ = 0.6 and wd = 3 rad/s. The steady-state error to a step input should be zero. Also, the steady state error to a ramp input should be 0.5. Assume that T = 0.2 s.
4.The block diagram of a sampled data control system is shown in Figure 9.30. Find the value of d.c. gain K to yield a damping ratio of 0.6
5.Draw the time response of the system in Exercise 4.
6.The open-loop transfer function of a system is
K
G(s) = .
0.2s + 1
The system is preceded by a sampler and a zero-order hold. The closed-loop system is required to have a time constant of 0.4 s. (a) Determine the required value of the d.c. gain K . (b) Plot the unit step time response of the system with the controller.
7.The block diagram of a system is given in Figure 9.31. It is required to design a controller for this system such that the system poles are at the points z1,2 = 0.4 ± j 0.4 in the z-plane.
(a)Derive the transfer function of the required digital controller. (b) Plot the unit step time response of the system without the controller. (c) Plot the unit step time response of the system with the controller.
8.The block diagram of a system is given in Figure 9.32. It is required to design a controller
for this system with percent overshoot (PO) less than 20 % and settling time ts ≤ 10 s. Assume that the sampling time is, T = 0.1 s.
(a)Derive the transfer function of the required digital controller.
(b)Draw the block diagram of the system together with the controller.
(c)Plot the unit step time response of the system without the controller.
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Figure 9.30 Block diagram for Exercise 4
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Figure 9.31 Block diagram for Exercise 7
EXERCISES 239
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Figure 9.32 Block diagram for Exercise 8
(d)Plot the unit step time response of the system with the controller.
9.Explain the differences between the position and velocity forms of the PID controller.
10.The open-loop unit step response of a system is shown in Figure 9.33. Obtain the transfer function of this system and use the Ziegler–Nichols tuning algorithm to design:
(a)a proportional controller;
(b)a PI controller;
(c)a PID controller.
Draw the block diagram of the system in each case.
11.Explain the procedure for designing a PID controller using the Ziegler–Nichols algorithm when the plant is open-loop.
12.Repeat Exercise 11 for the case when the plant is closed-loop. What precautions should be taken when tests are performed on a closed-loop system?
13.Explain what integral wind-up is when a PID controller is used. How can integral wind-up be avoided?
14.Explain what derivative kick is when a PID controller is used. How can derivative kick be avoided?
15.The open-loop transfer function of a unity feedback system is
95
10
Figure 9.33 Unit step response of the system for Exercise 10
240 |
DISCRETE CONTROLLER DESIGN |
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Figure 9.34 Block diagram for Exercise 17
Assume that T = 1 s and design a controller so that the system response to a unit step input is
y(k T ) = 0, 0.4, 1, 1, . . ..
16.A mechanical process has the transfer function K e−s TD /s The system oscillates with a frequency of 0.05 Hz when a unity gain feedback is applied. Determine the value of TD .
17.The block diagram of a system is given in Figure 9.34. It is required to design a controller
for this system with percent overshoot (PO) less than 15 % and settling time ts ≤ 10 s. Assume that the sampling time is, T = 0.2 s.
(a)Derive the transfer function of the required digital controller.
(b)Draw the block diagram of the system together with the controller.
(c)Plot the unit step time response of the system without the controller.
(d)Plot the unit step time response of the system with the controller.
18.Derive an expression for the z-transform model of the continuous-time PID controller. Draw the block diagram of the controller. Describe how you can modify the model to avoid derivative kick.
19.The continuous-time PI controller has the transfer function
U (s) = K p s + Ki .
E (s) s
Derive the equivalent discrete-time controller transfer function using the bilinear transformation.
20.A commonly used compensator in the s-plane is the lead lag, or lag lead with transfer function
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Find the equivalent discrete-time controller using the bilinear transformation.
FURTHER READING
[Dorf, 1974] |
Dorf, R.C. Modern Control Systems. Addison-Wesley Reading, MA, 1974. |
[Franklin et al., 1990] |
Franklin, G.F., Powell, J.D., and Workman, M.L. Digital Control of Dynamic Systems. |
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2nd edn., Addison-Wesley, Reading, MA, 1990. |
[Katz, 1981] |
Katz, P. Digital Control Using Microprocessors. Prentice Hall International, Engle- |
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wood Cliffs, NJ, 1981. |
10
Controller Realization
A control algorithm which takes the form of a z-transform polynomial must be realized in the computer in the form of a program containing unit delays, constant multipliers, and adders.
A given controller transfer function can be realized in many different ways. Mathematically the alternative realizations are all equivalent, differing only in the way they are implemented. Different realizations have different computational efficiencies, different sensitivities to parameter errors, and different programming efforts are needed in each case. Only some of the important realizations, such as the direct structure, cascaded structure and parallel structure, as well as the second-order structures, are described in this chapter.
10.1 DIRECT STRUCTURE
The transfer function D(z) of a digital controller can be represented in general by a ratio of two polynomials
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In direct structure the coefficients a j and b j appear as multipliers. There are several forms of direct structure, and we shall look at two of the most popular ones: the direct canonical structure and the direct noncanonical structure.
10.1.1 Direct Canonical Structure
Remembering that b0 = 1, we can rewrite (10.1) as
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Microcontroller Based Applied Digital Control D. Ibrahim
C 2006 John Wiley & Sons, Ltd. ISBN: 0-470-86335-8
244 CONTROLLER REALIZATION
Let us now introduce a variable R(z) such that
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Assume that the transfer function of a digital controller is
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Equations (10.8) and (10.9) define the direct form, and the block diagram of the implementation is shown in Figure 10.1. The controller is made up of delays, adders and multipliers. An example is given below.
Example 10.1
The transfer function of a digital controller is found to be
1 + 2z−1 + 4z−2 D(z) = 1 + 2z−1 + 5z−2 .
Draw the block diagram of the direct canonical realization of this controller.
Solution
With reference to (10.8), (10.9) and Figure 10.1, we can draw the required block diagram as in Figure 10.2.
z−1
rk−1
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a1
z−1
rk−2
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a2
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rk−n
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an
Figure 10.1 Canonical direct structure
10.1.2 Direct Noncanonical Structure
Consider Equation (10.2) with b0 = 1:
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Figure 10.2 Block diagram for Example 10.1
D(z) =
246 CONTROLLER REALIZATION
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Figure 10.3 Noncanonical direct structure
The block diagram of the noncanonical direct realization is shown in Figure 10.3. This structure has only one adder, but 2n delay elements.
Example 10.2
The transfer function of a digital controller is found to be
1 + 2z−1 + 4z−2 1 + 2z−1 + 5z−2 .
Draw the block diagram of the direct noncanonical realization of this controller.
Solution
With reference to (10.12) and Figure 10.3, we can draw the required block diagram as in Figure 10.4.
10.2 CASCADE REALIZATION
The cascade realization is less sensitive to coefficient sensitivity problems. In this method the transfer function is implemented as a product of first-order and second-order transfer functions. Thus, the controller transfer function is written as
D(z) =
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Figure 10.4 Block diagram for Example 10.2
−β
Figure 10.5 Realization of P (z)
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where m is the smallest integer greater than or equal to n/2.P (z) in (10.13) is the first-order transfer function
1 + α z−1
P (z) = 1 + β z−1 ,
shown in Figure 10.5. With reference to Figure 10.5, we can write
rk = ek − β rk−1
and
uk = rk + α rk−1.
Q(z) in (10.13) and (10.14) is a second-order transfer function,
Q(z) = a0 + a1z−1 + a2z−2 , 1 + b1z−1 + b2z−2
shown in Figure 10.6. With reference to Figure 10.6, we can write
rk = ek − b1rk−1 − b2rk−2
and
uk = a0rk + a1rk−1 + a2rk−2.
(10.15)
(10.16)
(10.17)
(10.18)
(10.19)
(10.20)
In practice, in order to avoid coefficient sensitivity problems second-order transfer function modules of the form given by (10.18) are frequently used and the modules are cascaded to give the required order. The block diagram of Figure 10.6 is sometimes drawn vertically, as shown in Figure 10.7.
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Figure 10.6 Realization of Q(z)
