MIPS_primery_zadach / dandamudi05gtr guide risc processors programmers engineers

Loading Constants

To specify constants in registers, the SPARC architecture provides a special instruction sethi (set high). It stores a 22-bit value in the upper 22 bits of the destination register. To facilitate constant manipulation, SPARC assemblers provide several unary operators to extract parts of a word or extended word. These operators are as follows.

We are now ready to see how we can use the sethi instruction to load integer constants into registers. First, let us look at 32-bit words. The instruction sequence

sethi %hi(value),Rd

or Rd,%lo(value),Rd

stores the 32-bit constant value in the Rd register. In fact, SPARC assemblers provide the pseudoinstruction

set value,Rd

to represent this two-instruction code sequence. If the upper 22 bits are zero, set uses

or %g0,value,Rd

On the other hand, if the lower 10 bits are zero, set uses

sethi %hi(value),Rd

The setx is similar to the set instruction except that it allows a 64-bit constant. The syntax is

setx value,Rt,Rd

This instruction stores the 64-bit constant value in Rd using Rt as a temporary register. This pseudoinstruction can be translated into a sequence of SPARC processor instructions by using %uhi, %ulo, %hi, and %lo unary operators along with or, sethi, and sllx instructions. The or and sllx instructions are discussed in the next section.

Arithmetic Instructions

The SPARC instruction set supports the basic four arithmetic operations. Most arithmetic operations have two versions: one version updates the condition codes and the other does not. In most instructions, the second operand can be a register or a signed 13-bit immediate imm13.

Add Instructions The SPARC instruction set provides add instructions with and without the carry. The instruction

add Rs1,Rs2,Rd

adds contents of Rs1 and Rs2 and stores the result in the Rd register. The immediate version of add is

add Rs1,imm13,Rd

The immediate value is sign-extended to 64 bits and added to the contents of Rs1. This instruction does not update the condition codes. If you want the operation to update the condition codes, use addcc instead of add. It updates the four integer condition codes mentioned before.

If you want to add the carry bit, use addc as shown below:

addc Rs1,Rs2,Rd

addccc Rs1,Rs2,Rd

These instructions add the icc carry bit. As usual, the second operand can be a signed 13-bit immediate value. These instructions are useful in multiword addition operations.

Subtract Instructions The SPARC instruction set has four subtract instructions corresponding to the four add instructions: sub, subcc, subc, and subccc. The last two subtract instructions subtract the icc carry bit. The format of these instructions is similar to that of the add instructions. The instruction

sub Rs1,Rs2,Rd

stores the result of Rs1−Rs2 in the destination register Rd.

Multiplication Instructions Unlike the other processors, the SPARC provides a single multiplication instruction for both signed and unsigned multiplication. The multiplication instruction

mulx Rs1,Rs2,Rd

multiplies two 64-bit values in Rs1 and Rs2 and places the 64-bit result in Rd. Strictly speaking, multiplying two 64-bit values can result in a 128-bit result. This instruction, however, provides only a 64-bit result. The input operands, obviously, should be restricted to get a valid result.

The 32-bit SPARC-V8 has two multiply instructions—one for the signed numbers and the other for unsigned numbers—as in the other processors we show in this book. The multiplication instructions do not modify any condition codes.

Division Instructions Two division instructions are available: udivx for unsigned numbers and sdivx for signed numbers. These instructions divide two 64-bit numbers and produce a 64-bit quotient. The format is

udivx Rs1,Rs2,Rd

sdivx Rs1,Rs2,Rd

These instructions place the result of Rs1÷Rs2 in the destination register Rd. As with the multiplication instructions, these instructions do not modify any of the condition codes. However, these instructions generate divide-by-zero exceptions. There is no remainder computed. As we show in the next chapter, the PowerPC also does not provide the remainder. However, we can easily compute the remainder as shown in the next chapter (page 90).

Logical Instructions

The three basic logical operations—and, or, and xor—are supported. These perform the bitwise logical operations. The instruction

and Rs1,Rs2,Rd

performs the bitwise AND operation (Rs1 AND Rs2) and stores the result in Rd.

The SPARC provides three additional logical operations: andn, orn, and xnor. The andn and orn operations negate the second operand before applying the specified logical operation. The xnor operation is equivalent to a NOT operation followed by an XOR operation.

If you want to update the condition codes, use the cc versions of these instructions. As before, the second operand can be a 13-bit signed constant.

Shift Instructions

Two types of shift instructions are provided: 32and 64-bit versions. The 64-bit versions use the suffix “x.” For example, sll is the 32-bit left-shift instruction, whereas sllx is the 64-bit version. Both leftand right-shift operations are supported. The instruction

sll Rs1,Rs2,Rd

left-shifts the lower 32 bits of Rs1 by the shift count specified by Rs2 and places the result in Rd. Note that only the least significant 5 bits of Rs2 are taken as the shift count.

The 64-bit version

sllx Rs1,Rs2,Rd

left-shifts the 64 bits of Rs1. The least significant 6 bits of Rs2 are taken as the shift count.

For all shift instructions, the second operand can also be a constant specifying the shift count. The format is

sll Rs1,count,Rd

The count is 5 bits long for 32-bit instructions and 6 bits long for the 64-bit versions. Use srl and srlx for logical right-shift and sra and srax for arithmetic right-

shift. For a discussion of the difference between the logical and arithmetic right-shift operations, see Chapter 15. The SPARC instruction set does not support rotate instructions.

Compare Instructions

The SPARC instruction set does not provide any compare instructions. However, SPARC assemblers provide a compare pseudoinstruction. The compare instruction

is implemented using the subcc instruction as

Branch Instructions

The SPARC instruction set provides test-and-jump as well as set-then-jump types of branch instructions. A discussion of these two types of branches is given in Chapter 2 (see page 24). The first group has six branch instructions. The simplest of these is shown below:

brz Rs1,target

This instruction jumps to the specified target if the contents of Rs1 are equal to zero. This transfer is achieved by updating the nPC register with the target address. When comparing, the values are treated as signed integers. The branch instructions are summarized in Table 5.2.

The set-then-jump branch instructions check the icc or xcc condition codes. The syntax is

bxxx i_or_x_cc,target

The xxx identifies the branch condition. The first operand specifies whether the icc or xcc condition codes should be used. The target address is specified as in the other branch instructions. Table 5.3 shows the branch instructions in this group.

It is a good time to talk about the branch delay slots used by most RISC processors. We have introduced the concept of the delay slot in Chapter 2 (see page 25). Consider the following C program fragment.

i = 10; x = 0;

while (i >= 0)

x = x + 35; /* loop body */ x = 2*x;

This code is translated into the following assembly language version.

improve efficiency by executing this instruction. The instruction slot after a branch is called the delay slot. Delay slots, however, require program modifications.

One simple solution to our problem is to do nothing (i.e., no operation) in the delay slot. We can correct our code to include a nop (no operation) instruction after each branch instruction, as shown below:

Even though we solved the problem, we defeated the purpose of the delay slot. The nop unnecessarily consumes processor cycles. This overhead can be substantial if the loop count is large. Branch instructions typically occur about 20% of the time, therefore we would be wasting a lot of processor cycles executing nop instructions.

We can avoid using the nops if we could move the instruction before the branch to after the branch instruction. In our code we could apply this strategy to the unconditional branch instruction brz. However, we cannot move the sub instruction after the conditional branch instruction brgez due to the dependence on the i0 register. The resulting code is shown below:

This is not a great improvement because we still have the main nop instruction in the loop body. We could improve this code further by noticing that the add and sub instructions at addresses 112 and 116 can be interchanged. Then we could move the add instruction after the brgz branch instruction, as shown below:

Procedure Instructions

Procedures in the SPARC can be invoked either by the call or jmpl instruction. The call instruction takes a label identifying the called procedure. The format is

call procName

As shown in Figure 5.3, the called procedure’s displacement is expressed as a 30-bit signed number. This displacement is PC-relative. The SPARC requires procedures to be word-aligned (i.e., the procedure address is a multiple of 4). It multiplies the 30-bit displacement value by 4 and adds to the contents of the PC to get the procedure address. As in the branch instructions, the call is also delayed. Thus, before the procedure is invoked, the instruction in the delay slot is executed. This delayed execution is achieved by placing the target address in the nPC.

To facilitate return from a procedure, the call instruction stores the PC value (i.e., address of the call instruction itself) in o7 (really r15). The following summarizes the actions taken by the call instruction.

nPC = PC + 4*30-bit displacement r15 = PC

The call instruction allows only direct addressing. The jmpl instruction allows more flexibility. It allows indirect procedure calls as well as the specification of a 32-bit target address. The format is

jmpl address,register

The target address can be specified in either of the two addressing modes allowed by the SPARC. It jumps to the 32-bit address given by address and leaves the current PC value, which is the address of the jmpl instruction itself, in register. To call a procedure indirectly, use

jmpl register,%r15

This causes transfer of control to the address in register and leaves the return address in r15 as in the call instruction.

We can also use the jmpl instruction to return from a procedure. For example, the instruction

jmpl %r15+8,%g0

adds 8 to the contents of r15 and delay jumps to that address. The current PC address is written to g0, which means it is ignored. We add 8 to the return address in r15 because r15 points to the call/jmpl instruction that called the procedure. Also, we have to skip the following delay-slot instruction. Assemblers typically provide a ret pseudoinstruction, which is translated into this particular jmpl instruction.

The SPARC also provides a return instruction that takes a return address as an operand. The format is

return address

For example, instead of the assembler-provided ret instruction, we can also use

return %r15+8

SPARC assemblers provide two pseudoinstructions (also called synthetic instructions) to facilitate return from procedures. The first return instruction

There is a special return instruction retl to return from a leaf procedure. A leaf procedure is a procedure that does not call any other procedure. The

We show an example use of these instructions later.

Parameter Passing

By convention, the first six arguments are passed in the out registers. The remaining arguments, if any, are passed via the stack. Recall that the caller’s eight out registers become the callee’s in registers. The following summarizes the usage of these registers.

The o6 is referred to as the stack pointer and can be accessed by its sp alias. The i6 is referred to as the frame pointer by the callee and we can use the alias fp to access it.

We can return up to six values via the registers as shown below: