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Compare immediate format

(c) Compare formats

Figure 7.2 Sample Itanium instruction formats (continued on the next page).

The Itanium supports three types of immediate formats: 8-, 14-, and 22-bit immediate values can be specified. In the immediate format, the sign of the immediate value is always placed in the fifth leftmost bit (the S bit in Figure 7.2b). When a 22-bit immediate value is specified, the destination register must be one of the first four registers (r0 through r3), as we have only two bits to specify this register.

In the branch instruction, the btype field indicates the type of branch instruction (e.g., branch on equality, less than, etc.). In the call instruction, the b1 field specifies the register that should receive the return address.

The integer load instruction formats are shown in Figure 7.2e. The x bit is used for opcode extension. In the indexed addressing mode, the 9-bit immediate value is split into three pieces: S, imm1, and imm7. The hint field, which gives the memory reference hint, is discussed later in this chapter.

Instruction-Level Parallelism

The Itanium enables instruction-level parallelism by letting the compiler/assembler explicitly indicate parallelism by providing run-time support to execute instructions in parallel, and by providing a large number of registers to avoid register contention. First we discuss the instruction groups, and then see how the hardware facilitates parallel execution of instructions by bundling nonconflicting instructions together.

Itanium instructions are bound into instruction groups. An instruction group is a set of instructions that do not have conflicting dependencies among them (read-after-write or write-after-write dependencies, as discussed later on page 115), and may execute in parallel. The compiler or assembler can indicate instruction groups by using the ;; notation. Let us look at a simple example to get an idea. Consider evaluating a logical expression consisting of four terms. For simplicity, assume that the results of these four logical terms are in registers r10, r11, r12, and r13. Then the logical expression in

if (r10 || r11 || r12 || r13) {

/* if-block code */

}

can be evaluated using or-tree reduction as

The first group performs two parallel or operations. Once these results are available, we can compute the final value of the logical expression. This final value in r3 can be used by other instructions to test the condition. Inasmuch as we have not discussed Itanium instructions, it does not make sense to explain these instructions at this point. We have some examples in a later section.

In any given clock cycle, the processor executes as many instructions from one instruction group as it can, according to its resources. An instruction group must contain at least one instruction; the number of instructions in an instruction group is not limited. Instruction groups are indicated in the code by cycle breaks (;;). An instruction group may also end dynamically during run-time by a taken branch.

register r3 provides the address. In the second instruction, contents of r3 and r2 are added to get the effective address. The third form uses a 9-bit signed immediate value, instead of register r2. In the last two forms, as explained earlier, the computed effective address is stored in r3.

The ldtype completer can be used to specify special load operations. For normal loads, the completer is not specified. For example, the instruction

loads eight bytes from the memory starting from the effective address in r6. As mentioned before, the Itanium supports speculative loads. Two example instructions are shown below:

We defer a discussion of these load instruction types to a later section that discusses the speculative execution model of Itanium.

The ldhint completer specifies the locality of the memory access. It can take one of the following three values.

A prefetch hint is implied in the two “update” forms of load instructions. The address in r3 after the update acts as a hint to prefetch the indicated cache line. In the “no update” form of load, r3 is not updated and no prefetch hint is implied. Level 1 refers to the cache level. Because we don’t cover temporal locality and cache memory in this book, we refer the reader to [6] for details on cache memory. It is sufficient to view the ldhint completer as giving a hint to the processor as to whether a prefetch is beneficial.

The store instruction is simpler than the load instruction. There are two types of store instructions, corresponding to the two addressing modes, as shown below:

The SZ completer can have four values as in the load instruction. The sttype can be none or rel. If the rel value is specified, an ordered store is performed. The sthint gives a prefetch hint as in the load instruction. However, it can be either none or nta. When no value is specified, temporal locality at level 1 is assumed. The nta has the same interpretation as in the load instruction.

Subtract Instructions The subtract instruction sub has the same format as the add instruction. The contents of register r3 are subtracted from the contents of r2. In the minus 1 form, the constant 1 is also subtracted. In the immediate form, imm is restricted to an 8-bit value.

The instruction shladd (shift left and add)

(qp) shladd r1 = r2,count,r3

is similar to the add instruction, except that the contents of r2 are left-shifted by count bit positions before adding. The count operand is a 2-bit value, which restricts the shift to 1-, 2-, 3-, or 4-bit positions.

Multiply Instructions Integer multiply is done using the xmpy and xma instructions. These instructions do not use the general registers; instead, they use the floating-point registers.

The xmpy instruction has the following formats.

The two source operands, floating-point registers f3 and f4, are treated either as signed or unsigned integers. The completer u in the second and fourth instructions specifies that the operands are unsigned integers. The other two instructions treat the two integers as signed. The l or h indicate whether the lower or higher 64 bits of the result should be stored in the f1 floating-point register.

The xmpy instruction multiplies the two integers in f3 and f4 and places the lower or upper 64-bit result in the f1 register. Note that we get a 128-bit result when we multiply two 64-bit integers.

The xma instruction has four formats as does the xmpy instruction, as shown below:

This instruction multiplies the two 64-bit integers in f3 and f4 and adds the zero-extended 64-bit value in f2 to the product.

Logical Instructions

Logical operations and, or, and xor are supported by three logical instructions. There is no not instruction. However, the Itanium has an and-complement (andcm) instruction that complements one of the operands before performing the bitwise-and operation.

All instructions have the same format. We illustrate the format of these instructions for the and instruction:

(qp) and r1 = r2,r3 (qp) and r1 = imm8,r3

The other three operations use the mnemonics or, xor, and andcm. The and-comple- ment instruction complements the contents of r3 and ands it with the first operand (contents of r2 or immediate value imm8).

Shift Instructions

Both leftand right-shift instructions are available. The shift instructions

(qp) shl r1 = r2,r3 (qp) shl r1 = r2,count

left-shift the contents of r2 by the count value specified by the second operand. The count value can be specified in r3 or given as a 6-bit immediate value. If the count value in r3 is more than 63, the result is all zeros.

Right-shift instructions use a similar format. Because right-shift can be arithmetical or logical depending on whether the number is signed or unsigned, two versions are available. The register versions of the right-shift instructions are shown below:

In the second instruction, the completer u is used to indicate the unsigned shift operation. We can also use a 6-bit immediate value for shift count as in the shl instruction.

Comparison Instructions

The compare instruction uses two completers as shown below:

(qp) cmp.crel.ctype p1,p2=r2,r3 (qp) cmp.crel.ctype p1,p2=imm8,r3

The two source operands are compared and the result is written to the two specified destination predicate registers. The type of comparison is specified by crel. We can specify one of 10 relations for signed and unsigned numbers. The relations “equal” (eq) and “not equal” (neq) are valid for both signed and unsigned numbers. For signed numbers, there are 4 relations to test for “<” (lt), “≤” (le), “>” (gt), and “≥” (ge). The corresponding relations for testing unsigned numbers are ltu, leu, gtu, and geu. The relation is tested as “r2 rel r3”.

The ctype completer specifies how the two predicate registers are to be updated. The normal type (default) writes the comparison result in the p1 register and its complement in the p2 register. This would allow us to select one of the two branches (we show an example on page 113). The ctype completer allows specification of other types such as and and or. If or is specified, both p1 and p2 are set to 1 only if the comparison result is 1; otherwise, the two predicate registers are not altered. This is useful for implementing or-type simultaneous execution. Similarly, if and is specified, both registers are set to 0 if the comparison result is 0 (useful for and-type simultaneous execution).

Branch Instructions

As in the other architectures, the Itanium uses branch instruction for traditional jumps as well as procedure call and return. The generic branch is supplemented by a completer to specify the type of branch. The branch instruction supports both direct and indirect branching. All direct branches are IP relative (i.e., PC relative). Some sample branch instruction formats are shown below:

IP Relative Form:

Indirect Form:

As can be seen, branch uses up to four completers. The btype specifies the type of branch. The other three completers provide hints and are discussed later.

For the basic branch, btype can be either cond or none. In this case, the branch is taken if the qualifying predicate is 1; otherwise, the branch is not taken. The IP-relative target address is given as a label in the assembly language. The assembler translates this into a signed 21-bit value that gives the difference between the target bundle and the bundle containing the branch instruction. The target pointer is to a bundle of 128 bits, therefore the value (target25−IP) is shifted right by 4 bit positions to get a 21-bit value. Note that the format shown in Figure 7.2d uses a 21-bit displacement value.

To invoke a procedure, we use the second form and specify call for btype. This turns the branch instruction into a condition call instruction. The procedure is invoked only if the qualifying predicate is true. As part of the call, it places the current frame marker and other relevant state information in the previous function state application register. The return link value is saved in the b1 branch register for use by the return instruction.

There is also an unconditional (no qualifying predicate) counted loop version. In this branch instruction (the third one), btype is set to cloop. If the Loop Count (LC) application register ar65 is not zero, it is decremented and the branch is taken.

We can use ret as the branch type to return from a procedure. It should use the indirect form and specify the branch register in which the call has placed the return pointer. In the indirect form, a branch register specifies the target address. The return restores the caller’s stack frame and privilege level.

The last instruction can be used for an indirect procedure call. In this branch instruction, the b2 branch register specifies the target address and the return address is placed in the b1 branch register.

Let us look at some examples of branch instructions. The instruction

transfers control to the instruction labeled skip, if the predicate register p3 is 1. The code sequence

mov lc = 100 loop_back:

. . .

br.cloop loop_back

executes the loop body 100 times. A procedure call may look like

(p0) br.call br2 = sum

whereas the return from procedure sum uses the indirect form

(p0) br.ret br2

Because we are using predicate register 0, which is hardwired to 1, both the call and return become unconditional.

The bwh (branch whether hint) completer can be used to convey whether the branch is taken (see page 119). The ph (prefetch hint) completer gives a hint about sequential prefetch. It can take either few or many. If the value is few or none, few lines are prefetched; many lines are prefetched when many is specified. The two levels—few and many—are system defined. The final completer dh (deallocation hint) specifies whether the branch cache should be cleared. The value clr indicates deallocation of branch information.

Handling Branches

Pipelining works best when we have a linear sequence of instructions. Branches cause pipeline stalls, leading to performance problems. How do we minimize the adverse effects of branches? There are three techniques to handle this problem.

•Branch Elimination: The best solution is to avoid the problem in the first place. This argument may seem strange as programs contain lots of branch instructions. Although we cannot eliminate all branches, we can eliminate certain types of branches. This elimination cannot be done without support at the instruction-set level. We look at how the Itanium uses predication to eliminate some types of branches.

•Branch Speedup: If we cannot eliminate a branch, at least we can reduce the amount of delay associated with it. This technique involves reordering instructions so that instructions that are not dependent on the branch/condition can be executed while the branch instruction is processed. Speculative execution can be used to reduce branch delays. We describe the Itanium’s speculative execution strategies later.