MIPS_primery_zadach / dandamudi05gtr guide risc processors programmers engineers

R−Type (Register)

Figure 4.2 The MIPS instruction formats.

The use of a limited number of instruction formats simplifies instruction decoding. However, three instruction formats and a single addressing mode mean that complicated operations and addressing modes will have to be synthesized by the compiler. If these operations and addressing modes are less frequently used, we may not pay much penalty. This is the motivation behind the RISC processors.

Memory Usage

The MIPS uses a conventional memory layout. A program’s address space consists of three parts: code, data, and stack. The memory layout of these three components is shown in Figure 4.3. The text segment, which stores instructions, is placed at the bottom of the user address space at 0x4000000.

The data segment is placed above the text segment and starts at 0x10000000. The data segment is divided into static and dynamic areas. The dynamic area grows as memory is allocated to dynamic data structures.

The stack segment is placed at the end of the user address space at 0x7FFFFFFF. It grows downward towards the lower memory address. This placement of segments allows sharing of unused memory by both data and stack segments.

Memory addresses (in hex)

7FFFFFFF

Stack segment

Dynamic area

Data segment

Static area

10000000

Text segment

4000000

Reserved

0

Figure 4.3 MIPS memory layout.

Summary

We have presented the basic details of the MIPS architecture. The MIPS32 architecture provides 32 general-purpose registers, a program counter register, and two specialpurpose registers. Each register is 32 bits long. The two special-purpose registers are used by the multiply and divide instructions. MIPS effectively supports only a single addressing mode.

We have not discussed the MIPS instruction set and other details here. We devote the next part of the book to this purpose. In the remainder of this part, we look at a few other RISC architectures.

Web Resources

MIPS32 documentation is available from the MIPS Web site. The MIPS32 Architecture for Programmers, which consists of three volumes, describes the 32-bit MIPS architecture in detail [16, 17, 18]. If you are interested in the 64-bit architecture, it is also de-

scribed in a three-volume manual MIPS64 Architecture for Programmers [19, 20, 21]. These manuals are available from www.mips.com/content/Documentation/ MIPSDocumentation.

In this chapter, we present details about the 64-bit version. Like the MIPS, it also uses the load/store architecture we discussed in Chapter 2. We start our discussion with the register set. The following sections cover the addressing mode and instruction set details.

Registers

The SPARC register set organization is different from the MIPS architecture discussed in the last chapter. At any time, a user’s program sees 32 general-purpose 64-bit registers r0 through r31. These 32 registers are divided into four groups of eight registers each, as shown in Figure 5.1. As in the MIPS architecture, register zero r0 is hardwired to constant zero.

General-purpose registers r0 to r7 are used as the global registers. It also maintains another set of eight alternate global registers (see Figure 5.2). The AG (Alternate Global) field of the Processor State (PSTATE) register determines which global register set is used. By keeping global variables in the global registers, we can completely avoid accessing memory for procedure calls and returns. A similar mechanism is also used by the Itanium.

The SPARC architecture uses the register windows shown in Figure 5.2. A register window has 24 registers consisting of in, local, and out registers. The out registers of one set overlap the in registers of the adjacent set. This reduces the overhead in parameter passing. The Current Window Pointer (CWP) register gives the current window information. The value of CWP can be incremented or decremented by two instructions: the restore instruction decrements the CWP register, and the save instruction increments it. We give details of these two instructions later.

An implementation may have from 64 to 528 registers. Thus, in an implementation with the minimum number of 64 registers, we can have three register sets (8 global, 8 alternate global, three sets of 16 registers each). When the maximum number of registers is implemented, we can have 32 register sets. An implementation can define NWINDOWS to specify the number of windows, which ranges from 3 to 32. These window sets are organized as a circular buffer. Thus, the CWP arithmetic is done modulo NWINDOWS.

Condition Code Register This register provides two 4-bit integer condition code fields: xcc and icc. Each field consists of four bits, as shown below:

The n bit sign flag records whether the result of the last instruction that affects the condition codes is negative (n = 1) or positive (n = 0). The xcc condition codes record status information about the result of an operation when the operands are 64 bits (the “x” stands for extended). The icc records similar information for 32-bit operands. For example, if the result is 00000000F000FFFFH, the n bit of icc is set because the 32-bit result is a negative number. However, the 64-bit result is positive; therefore, the n bit is cleared.

Figure 5.2 Register windows in the SPARC architecture.

Addressing Modes

The SPARC architecture supports the two addressing modes we discussed in Chapter 2: the register indirect with index and register indirect with immediate addressing modes.

•Register Indirect with Immediate: This addressing mode is similar to the MIPS addressing mode discussed in the last chapter. It computes the effective address as

Effective address = contents of Rx + imm13.

The base register Rx can be any general-purpose register. A 13-bit signed constant imm13 can be specified as the displacement. This constant is sign-extended to 64 bits and added to the Rx register (see our discussion on sign extension in Appendix A).

•Register Indirect with Index: This addressing mode computes the effective address as the sum of two register contents.

Effective address = contents of Rx + contents of Ry.

The base register Rx and the index register Ry can be any general-purpose registers.

There is no register indirect addressing mode in which the contents of a register are taken as the effective address. But we can emulate this addressing mode by making the constant zero in the first addressing mode, or using r0 as the index register in the second addressing mode. Note that r0 is hardwired to read zero.

Instruction Format

All SPARC instructions are 32 bits long. The instruction format uses two opcode fields: the most significant two bits op (bits 30 and 31) identify a major operation group and the second field, op2 or op3, specifies the actual instruction. A sample of the instruction formats is shown in Figure 5.3. The first two formats show how most instructions that use three addresses are encoded. If an immediate value is used, the second format is used. The i bit specifies whether one of the source operands is in a register (i = 0) or a constant (i = 1).

The next three formats are used for sethi and conditional branch instructions. The sethi instruction moves a 22-bit constant into a register (see page 62). The SPARC architecture supports two types of conditional branch instructions. These branch instructions are also discussed later.

The final format is used for procedure calls. We can specify a 30-bit signed displacement value as part of this instruction.

Instruction Set

This section gives details about the SPARC instruction set. Procedure invocation and parameter-passing details are discussed in the next section.

Data Transfer Instructions

Because the SPARC follows the load/store architecture, only load and store instructions can move data between a register and memory. The load instruction

Call instructions

Figure 5.3 Some sample SPARC instruction formats.

ldsb [address],Rd

loads the signed byte in memory at address into the Rd register. Because it is a signed byte, it is sign-extended to 64 bits and loaded into Rd. To load signed halfword and word, use ldsh and ldsw, respectively. The corresponding unsigned load instructions are ldub, lduh, and lduw. These instructions zero-extend the data to 64 bits before loading into the Rd register. To load a 64-bit extended word, use ldx.