MIPS_primery_zadach / dandamudi05gtr guide risc processors programmers engineers

Count Register

The 64-bit CTR register holds the loop count value. Branch instructions can specify a variety of conditions under which branching should take place. For example, a conditional branch instruction can decrement CTR and branch only if CTR =0 or if CTR = 0. Even more complex branch conditions can be tested. More details on the branch instruction are presented later in this chapter (page 93).

XER Register

The XER register serves two distinct purposes. Bits 0, 1, and 2 are used to record Summary Overflow (SO), OVerflow (OV), and CArry (CA). The OV bit records the fact that an overflow has occurred during the execution of an instruction. The SO bit is different in the sense that it is set whenever the OV bit is set. However, once set, the SO bit remains set until a special instruction is executed to clear it. The CA bit is set by add and subtract arithmetic operations and right-shift instructions.

Bits 57 to 63 are used as a 7-bit byte count to specify the number of bytes to be transferred between memory and registers. This field is used by Load String Word Indexed (lswx) and Store String Word Indexed (stswx) instructions. Using just one lswx instruction we can load 128 contiguous bytes from memory into all 32 general-purpose registers. Similarly, reverse transfer can be done by stswx instruction.

Addressing Modes

The PowerPC supports two basic addressing modes as does the SPARC. We can specify three general-purpose registers rA, rB, and rD/rS in load/store instructions. Registers rA and rB are used to compute the effective address. The third register is treated either as the destination register rD in load operations or as the source register rS in store operations.

Register Indirect with Immediate

In this addressing mode, instructions contain a signed immediate value imm. The effective address is computed by adding this value to the contents of a general-purpose register rA specified in the instruction. Interestingly, we can specify a 0 in place of rA. In this case, the effective address is the immediate value given in the instruction. Thus, it is straightforward to convert indirect addressing to direct addressing.

Effective address = Contents of rA or 0 + imm

The immediate constant is either 14 or 16 bits depending on the instruction encoding used. We discuss instruction formats in the next section. Also, note that this is the only addressing supported by the MIPS architecture.

Register Indirect with Index

Instructions using this addressing mode specify two general-purpose registers rA and rB. The effective address is computed as the sum of the contents of these two registers. As in the other addressing modes, we can specify 0 in place of rA.

Effective address = Contents of rA or 0 + Contents of rB

These addressing modes are also available in the update version. In this version, the computed effective address is loaded into the base register rA. We look at these two versions next.

Register Indirect with Immediate Update

This is the update version of the first addressing mode. The semantics are shown below:

Effective address = Contents of rA or 0 + imm rA = Effective address

Register Indirect with Index Update

The indexed version has the following semantics.

Effective address = Contents of rA or 0 + Contents of rB rA = Effective address

We later show how these update versions are useful in accessing arrays by means of an example.

In our discussion so far, we assumed 64-bit mode. In 32-bit mode, computation of the effective address is the same. However, only the lower-order 32 bits are used as the effective address to access memory.

Instruction Format

As with the MIPS and SPARC, all PowerPC instructions are encoded using four bytes. Instructions are assumed to be word-aligned, so that the processor can ignore the least significant two bits of all instruction addresses.

As shown in Figure 6.3, bits 0 to 5 specify the primary opcode. Many instructions also have an extended opcode. The remaining bits are used for various fields depending on the instruction type. Here we discuss some basic instruction formats.

Most instructions use the register format shown in Figure 6.3a. In arithmetic, logical, and other similar instruction types, registers rA and rB specify the source operands and rD specifies the destination register. The OE and rC bits are explained later.

The immediate format shown in Figure 6.3b is used by instructions that specify an

Register indirect with indexing mode (X−form)

(d) Load/store format

Figure 6.3 Sample PowerPC instruction formats.

immediate operand. For example, the addi instruction, described in the next section, uses this format.

The format shown in Figure 6.3c is used by branch instructions. The unconditional branch format allows specification of a 24-bit target address. This figure also shows the format used by direct and indirect conditional branch instructions. The AA bit is used to

indicate whether the address is an absolute address or a relative address. The LK bit is used to link the return address so that we can use the branch instruction for procedure calls. More details on the branch instruction fields, including the BO and BI fields, are given later in this chapter (page 94).

The format of load/store instructions is shown in Figure 6.3d. The first format is used by load/store instructions that specify the address in the first addressing mode. As mentioned before, these instructions use rA and the signed 16-bit operand (imm) to compute the effective address. The second format is used by load/store instructions that use the index addressing mode (i.e., the second addressing mode).

Note that we have skipped several other formats used by the PowerPC to encode instructions. The PowerPC manual [23] contains a more detailed description of these instruction formats.

Instruction Set

This section presents a sample of the PowerPC instructions. As in the last chapter, we organize our presentation into instruction groups. Let us begin with the data transfer instructions.

Data Transfer Instructions

The PowerPC instruction set supports a variety of load and store instructions to move data between memory and registers. We discuss some of these instructions to convey the type of instructions available. The load and store instructions do not affect any of the status bits. There are no instructions to move data between registers. However, we can use a logical instruction to affect such moves. We give an example of this later.

Load Instructions Load instructions operate on byte, half-word, word, and doubleword data. Note that load instructions that operate on floating-point numbers are also available, but we do not discuss them here. The following is a list of load instructions that work on byte data.

The first instruction lbz loads the byte at the Effective Address (EA) into the lower-order byte of rD. The remaining three bytes in rD are cleared (i.e., zeroed). The EA is computed as the sum of the contents of rA and the displacement disp. Note that if we specify 0 for rA, disp becomes the effective address.

The second instruction lbzu performs the same operation as the lbz instruction. In addition, it loads the computed effective address into rA (i.e., it updates rA with EA).

The last two instructions use the indexed addressing mode. The effective address is computed as the sum of the contents of registers rA and rB. Except for the computation of the EA, lbzx is similar to the lbz instruction, and lbzxu is similar to the lbzu instruction.

The update forms of these instructions are useful to access arrays. For example, suppose that rA initially points to an array of bytes and disp is 1. We can use lbzu to access successive bytes from this array by repeatedly executing this instruction. There is no need to update the array pointer. If we want to access every 4th element of this array, all we have to do is change disp value to 4.

To move halfwords, there are four instructions corresponding to the four-byte load instructions. Halfword instructions use the mnemonics lhz, lhzu, lhzx, and lhzux. Similarly, word instructions use the mnemonics lwz, lwzu, lwzx, and lwzux.

When loading halfwords, instead of zeroing the upper two bytes, we can also signextend halfword to word (see our discussion in Appendix A). Remember that sign extension copies the sign bit to the remaining higher-order bits. We can use the following load instructions to sign-extend the halfword in rD:

Similar instructions for loading words are also available. The mnemonics for these instructions are lwa, lwax, and lwaux. Finally, the instructions ld, ldu, ldx, and ldux can be used to load doublewords.

The PowerPC provides some interesting multiword load instructions. As an example, consider the instruction:

It loads n consecutive words from memory starting at EA, which is computed as in the previous instructions. Inasmuch as the target is a register, what is n? This instruction loads words starting with rD and proceeds until r31. Note that it loads only the lower-order 32 bits in each register. For example, if we specify r20 as rD, 12 consecutive words from memory are loaded into lower-order 32 bits of registers r20, r21, . . . , r31.

Store Instructions There is a store instruction corresponding to each load instruction to move data to memory. For example, to move a byte into memory, these instructions can be used:

There are corresponding instructions to store halfwords: sth, sthu, sthx, and sthux. Similar instructions are available to store words and doublewords (just substitute “w” for words and “d” for doublewords in the mnemonics for the byte instructions).

To store multiple words, we can use the following:

This instruction has the same semantics as the lmw instruction except for the direction of data movement. As in the lmw instruction, it loads the lower-order 32 bits from these registers.

Arithmetic Instructions

The PowerPC supports the four basic arithmetic instructions: add, subtract, multiply, and divide. We start our discussion with the addition instructions.

Addition Instructions The basic add instruction

add rD,rA,rB

adds contents of registers rA and rB and stores the result in rD. Status and overflow bits of the CR0 field as well as the XER register are not altered. Three variations on the basic add are possible to affect these bits:

The OE bit in Figure 6.3a indicates whether the SO and OV bits of the XER register are altered (OE = 1) or not (OE = 0). Thus, this bit is set for the last two add instructions (addo and addo.) and cleared for the other two instructions.

The rc bit specifies if the LT, GT, and EQ bits of CR0 field should be altered. This bit is set for those instructions that alter these bits. Thus, rc = 1 for the two “dot” versions of the add instruction (add. and addo.).

These four add instructions do not affect the CA bit in the XER register. To alter the carry bit, we have to use addc, addc., addco, and addco. instructions. The other bits are updated as in the basic add instruction variations. Yet another variation is the adde instruction. The instruction

adde rD,rA,rB

adds contents of registers rA, rB and the CA bit of the XER register. As usual, the result goes into the rD register. As with the add instruction, it does not alter any of the status bits. We can use adde., addeo, or addeo. to affect these status and condition bits. The addc and adde instructions are useful in performing multiword addition operations.

We can also have an immediate operand specified in an add instruction. The add instruction

to get the higher-order 32 bits of the result.

For unsigned numbers, we have to use mulhwu instead of mulhw to get the higherorder 32 bits of the result. The lower-order 32 bits are given by mullw for both signed and unsigned integers.

There is also a multiply immediate instruction that takes an immediate value. The format is

mulli rD,rA,Simm16

The immediate value Simm16 is a 16-bit signed integer. Note that this operation produces a 48-bit result. But the mulli instruction stores only the lower 32 bits of the result.

Divide Instructions Like the multiply operation, two divide instructions—one for signed integers and the other for unsigned integers—are provided. The instruction

stores the quotient of rA/rB in rD. The operands are treated as signed integers. The remainder is not available. To get both quotient and remainder, we have to use the following three-instruction sequence.

For unsigned integers, use the divwu (divide word unsigned) instruction instead.

Logical Instructions

The PowerPC instruction set has several logical instructions including and, or, nor, nand, equ, and xor instructions. It does not have the not instruction; however, the not operation can be implemented using the nor instruction. These instructions have a similar format, therefore we discuss the complete set of and instructions available in the PowerPC instruction set.

The and instruction performs bitwise AND of rS and rB and places the result in the rA register. The condition register field CR0 is not affected. The and. instruction is similar to and but updates the LT, GT, and EQ bits of the CR0 field. This is true with all the instructions ending in a period. The andi takes a 16-bit unsigned integer as one of the source operands. The andis. instruction is similar to andi. except that the immediate

value is left-shifted by 16 bit positions before ANDing. Note that the shifted-out bits on the right receive zeros. In the andc instruction, the contents of rB are complemented before performing the and operation.

The logical or instruction also has six versions as does the and instruction. The only difference is that the immediate versions do not update the CR0 field. That is, the immediate or instructions are ori and oris with no period. We can use the or instruction to move register contents as shown below:

A no-operation (nop) is implemented as

ori 0,0,0

The NAND instructions (nand and nand.) perform a NOT operation followed by an AND operation. Similarly, NOR instructions (nor and nor.) perform a NOT operation after an OR operation.

The PowerPC instruction set also includes four xor instructions as shown below:

The semantics of these four instructions are similar to the and instructions, except for the actual operation performed.

In addition, the PowerPC provides the eqv (equivalence) logical function. The equivalence function is defined as the exclusive-NOR operation (i.e., the output of XOR is complemented). Two instructions—eqv and eqv.— are available.

Shift Instructions

The PowerPC provides four types of shift instructions to shift left or right. Each type of instruction is available in two forms: one that does not affect the status bits in CR0 and the other that updates these status bits (i.e., the “dot” version). We first discuss the left-shift instruction. The sld (shift left doubleword) instruction

sld rA,rS,rB

left-shifts the contents of rS by the shift count value specified in rB, and the result is placed in rA. Shifted-out bits on the right receive zeros. For the shift count, only the least significant seven bits are taken from the rB register. If the shift count is between 64 and 127, the result is zero. We can use sld. to update the status bits in CR0.

There are two shift right instructions—srd and srd.—that are similar to the two left-shift instructions except for the direction of shift. Zeros replace the vacated bits on the left. These two right-shift instructions perform logical shift operations. In logical shifts, vacated bits receive zeros. On the other hand, in an arithmetic right-shift operation, vacated bits receive the sign bit. For details on the differences and the need for logical