Introduction

1.1About the ARM7TDMI core

The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit microprocessors. The ARM family offers high performance for very low power consumption, and small size.

The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles. The RISC instruction set, and related decode mechanism are much simpler than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:

•a high instruction throughput

•an excellent real-time interrupt response

•a small, cost-effective, processor macrocell.

This section describes:

•The instruction pipeline

•Memory access on page 1-3

•Memory interface on page 1-3.

•EmbeddedICE Logic on page 1-3.

1.1.1The instruction pipeline

The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions to the processor. This allows several operations to take place simultaneously, and the processing and memory systems to operate continuously.

A three-stage pipeline is used, so instructions are executed in three stages:

•Fetch

•Decode

•Execute.

Figure 1-1 Instruction pipeline

Introduction

During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The program counter points to the instruction being fetched rather than to the instruction being executed. This is important because it means that the Program Counter (PC) value used in an executing instruction is always two instructions ahead of the address.

1.1.2Memory access

The ARM7TDMI core has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory.

Data can be:

•8-bit (bytes)

•16-bit (halfwords)

•32-bit (words).

Words must be aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte boundaries.

1.1.3Memory interface

The ARM7TDMI processor memory interface has been designed to allow performance potential to be realized, while minimizing the use of memory. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic. These control signals facilitate the exploitation of the fast-burst access modes supported by many on-chip and off-chip memory technologies.

The ARM7TDMI core has four basic types of memory cycle:

•idle cycle

•nonsequential cycle

•sequential cycle

•coprocessor register transfer cycle.

1.1.4EmbeddedICE Logic

EmbeddedICE Logic is the additional hardware provided by debuggable ARM processors to aid debugging. It allows software tools to debug code running on a target processor. The EmbeddedICE Logic is controlled through the Joint Test Action Group (JTAG) test access port, using the EmbeddedICE interface. See Chapter 5 Debug Interface and Appendix B Debug in Depth for more information.