Debug Interface

5.2Debug systems

Figure 5-1 shows a typical debug system using an ARM core.

Host computer running

Debug host ARM or third party toolkit

Development system

Debug target containing an

ARM7TDMI processor

Figure 5-1 Typical debug system

A debug system typically has three parts:

•Debug host

•Protocol converter

•Debug target on page 5-5.

The debug host and the protocol converter are system-dependent.

5.2.1Debug host

The debug host is a computer that is running a software debugger such as the ARM Debugger for Windows (ADW). The debug host allows you to issue high-level commands such as setting breakpoints or examining the contents of memory.

5.2.2Protocol converter

The protocol converter communicates with the high-level commands issued by the debug host and the low-level commands of the ARM7TDMI processor JTAG interface. Typically it interfaces to the host through an interface such as an enhanced parallel port.

Debug Interface

The ARM7TDMI processor has hardware extensions that ease debugging at the lowest level. The debug extensions:

•allow you to halt program execution

•examine and modify the core internal state of the core

•view and modify the state of the memory system

•resume program execution.

5.2.3Debug target

The major blocks of the debug target are shown in Figure 5-2.

The ARM CPU core

This has hardware support for debug.

The EmbeddedICE Logic

This is a set of registers and comparators used to generate debug exceptions such as breakpoints. This unit is described in About EmbeddedICE Logic on page 5-13.

The TAP controller

This controls the action of the scan chains using a JTAG serial interface.