AC and DC Parameters

7.19Boundary scan general timing

Figure 7-18 shows the ARM7TDMI processor boundary scan general timing. The timing parameters used in Figure 7-18 are listed in Table 7-18.

TCK

AC and DC Parameters

7.20Reset period timing

Figure 7-19 shows the ARM7TDMI reset period timing. The timing parameters used in Figure 7-19 are listed in Table 7-19.

nRESET

Trstl

nTRST

Tbsr

D[31:0]

Figure 7-19 Reset period timing

Table 7-19 Reset period timing parameters

AC and DC Parameters

7.21Output enable and disable times

Figure 7-20 shows the output enable and disable times due to a HIGHZ TAP instruction. Figure 7-21 shows the output enable and disable times due to data scanning.The timing parameters used in Figure 7-20 and Figure 7-21 are listed in Table 7-20.

TCK

A[ ]

D[ ]

Figure 7-20 Output enable and disable times due to HIGHZ TAP instruction

Note

Figure 7-20 shows the Tbse, output enable time, parameter and Tbsz, output disable time, when the HIGHZ TAP instruction is loaded into the instruction register.

TCK

A[ ]

D[ ]

Figure 7-21 Output enable and disable times due to data scanning

Note

Figure 7-21 shows the Tbse, output enable time, parameter and Tbsz, output disable time when data scanning, due to different logic levels being scanned through the scan cells for ABE and DBE.

Table 7-20 Output enable and disable timing parameters

AC and DC Parameters

7.22Address latch enable control

Figure 7-22 shows the ARM7TDMI reset period timing. The timing parameters used in Figure 7-22 are listed in Table 7-21.

Phase 1 Phase 2

MAS[1:0]

Figure 7-22 ALE control timing

Note

In Figure 7-22, Tald is the time by which ALE must be driven LOW to latch the current address in phase 2. If ALE is driven LOW after Tald, then a new address is latched. This is known as address breakthrough.

Table 7-21 ALE address control timing parameters