Debug Interface

5.5Determining the core and system state

When the core is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline.

Before you can examine the core and system state, the debugger must determine whether the processor entered debug from Thumb state or ARM state, by examining bit 4 of the EmbeddedICE Logic debug status register. When bit 4 is HIGH, the core has entered debug from Thumb state.

For more details about determining the core state, see Determining the core and system state on page B-24.

Debug Interface

5.6About EmbeddedICE Logic

The ARM7TDMI processor EmbeddedICE Logic provides integrated on-chip debug support for the ARM7TDMI core.

The EmbeddedICE Logic is programmed serially using the ARM7TDMI processor TAP controller. Figure 5-5 illustrates the relationship between the core, EmbeddedICE Logic, and the TAP controller, showing only the pertinent signals.

Figure 5-5 ARM7TDM, TAP controller, and EmbeddedICE Logic

The EmbeddedICE Logic comprises:

•two real-time watchpoint units

•two independent registers:

— the debug control register

Debug Interface

— debug status register.

•Debug Communications Channel (DCC).

The debug control register and the debug status register provide overall control of

EmbeddedICE operation.

You can program one or both watchpoint units to halt the execution of instructions by the core. Execution halts when the values programmed into EmbeddedICE match the values currently appearing on the address bus, data bus, and various control signals.

Note

You can mask any bit so that its value does not affect the comparison.

You can configure each watchpoint unit for either a watchpoint or a breakpoint.

Watchpoints and breakpoints can be data-dependent.

Debug Interface

5.7Disabling EmbeddedICE

The EmbeddedICE Logic is disabled by setting DBGEN LOW.

Caution

Hard-wiring the DBGEN input LOW permanently disables the EmbeddedICE Logic. However, you must not rely upon this for system security.

When DBGEN is LOW:

•BREAKPT and DBGRQ are forced LOW to the core

•DBGACK is forced LOW from the ARM7TDMI core

•interrupts pass through to the processor uninhibited by the debug logic

•EmbeddedICE Logic is put into a low-power mode.