Chapter 6

Instruction Cycle Timings

This chapter describes the ARM7TDMI processor instruction cycle operations. It contains the following sections:

•About the instruction cycle timing tables on page 6-3

•Branch and branch with link on page 6-4

•Thumb branch with link on page 6-5

•Branch and Exchange on page 6-6

•Data operations on page 6-7

•Multiply and multiply accumulate on page 6-9

•Load register on page 6-12

•Store register on page 6-14

•Load multiple registers on page 6-15

•Store multiple registers on page 6-17

•Data swap on page 6-18

•SSoftware interrupt and exception entry on page 6-19

•Coprocessor data operation on page 6-20

•Coprocessor data transfer from memory to coprocessor on page 6-21

•Coprocessor data transfer from coprocessor to memory on page 6-23

•Coprocessor register transfer, load from coprocessor on page 6-25

Instruction Cycle Timings

•Coprocessor register transfer, store to coprocessor on page 6-26

•Undefined instructions and coprocessor absent on page 6-27

•Unexecuted instructions on page 6-28

•Instruction speed summary on page 6-29.

Instruction Cycle Timings

6.1About the instruction cycle timing tables

In the following tables:

•nMREQ and SEQ, are pipelined up to one cycle ahead of the cycle to which they apply. They are shown in the cycle in which they appear and indicate the next cycle type.

•The address, MAS[1:0], nRW, nOPC, nTRANS, and TBIT signals, that appear up to half a cycle ahead, are shown in the cycle to which they apply. The address is incremented to prefetch instructions in most cases. Because the instruction width is four bytes in ARM state and two bytes in Thumb state, the increment varies accordingly.

•The letter L is used to indicate instruction length:

—four bytes in ARM state

—two bytes in Thumb state.

•The letter i is used to indicate the width of the instruction fetch output by

MAS[1:0]:

—i=2 in ARM state represents word accesses

—i=1 in Thumb state represents halfword accesses.

•Terms placed inside brackets represent the contents of an address.

•The • symbol indicates zero or more cycles.

Instruction Cycle Timings

6.2Branch and branch with link

A branch instruction calculates the branch destination in the first cycle, while performing a prefetch from the current PC. This prefetch is done in all cases because, by the time the decision to take the branch has been reached, it is already too late to prevent the prefetch.

During the second cycle a fetch is performed from the branch destination, and the return address is stored in register 14 if the link bit is set.

The third cycle performs a fetch from the destination +L, refilling the instruction pipeline. If the instruction is a branch with link (R14 is modified) four is subtracted from R14 to simplify the return instruction from SUB PC,R14,#4 to MOV PC,R14. This allows subroutines to push R14 onto the stack and pop directly into PC upon completion.

The cycle timings are listed in Table 6-1 where:

•pc is the address of the branch instruction

•alu is the destination address calculated by the ARM7TDMI core

•(alu) is the contents of that address.

Table 6-1 Branch instruction cycle operations

Note

Branch with link is not available in Thumb state.