Index

entry into on breakpoint 5-7 entry into on debug request 5-8 entry into on watchpoint 5-8 exit B-26

exit sequence B-28 function and mapping of

EmbeddedICE registers B-40 host 5-4

ID code register B-14 instruction register B-8, B-15 interface 5-2

interface signals 5-6 interrupt driven use of comms

channel 5-18 mask registers B-42

output enable and disable times due to HIGHZ TAP instruction 7-25

priorities and exceptions B-32 Data Aborts B-32 interrupts B-32

Prefetch Abort B-32 programming restriction B-55 protocol converter 5-4

public instructions B-9 BYPASS B-12 CLAMP B-11 CLAMPZ B-11 EXTEST B-9 HIGHZ B-11 IDCODE B-12 INTEST B-12 RESTART B-10

SAMPLE/PRELOAD B-10 SCAN_N B-10

receiving a message from debugger 5-18

request B-30

reset period timing 7-24 return address calculation B-31 scan chain 0 B-18

scan chain 0 cells B-33 scan chain 1 B-19 scan chain 1 cells B-37 scan chain 2 B-19 scan chain 3 B-20 scan chains B-16

scan path select register B-15 sending a message to debugger 5-17 stages 5-2

state 3-31

status register B-50 system sppeed access B-31 system state B-24

systems 5-4 target 5-5

test data registers B-14 bypass B-14

ID code B-14 instruction B-15 scan path select B-15

timing 7-17

watchpoint registers B-40 programming and reading B-41

watchpoint with another exception B-30

watchpoints B-29 programming B-47

Depipelined address timings 3-15

E

EmbeddedICE logic 5-13 registers

function and mapping B-40 timing B-54

EmbeddedICE Logic 1-3 disabling 5-15

Exception timing 7-15

Exception entry/exit summary 2-16 Exception priorities 2-22 Exception vectors 2-21 Exceptions 2-16

abort 2-19 data 2-20

prefetch 2-20 entering 2-17 FIQ 2-18

IRQ 2-19 leaving 2-18 SWI 2-21

undefined instruction 2-21 External bus arrangement 3-17 External connection of unidirectional

buses 3-19

External coprocessors 4-15

F

FIQ mode 2-7

H

Halfword accesses 3-26, 3-27

I

ID code register B-14 Instruction cycle timings

branch 6-4

branch and exchange 6-6 branch with link 6-4 coprocessor absent 6-27 coprocessor data operation 6-20 coprocessor data transfer 6-21

coprocessor register transfer 6-25 data operations 6-7

data swap 6-18 exceptions 6-19

instruction speed summary 6-29 load multiple registers 6-15 load register 6-12

multiply 6-9

multiply accumulate 6-9 store multiple registers 6-17 store register 6-14

SWI 6-19

Thumb branch with link 6-5 undefined instructions 6-27 unexecuted instructions 6-28

Instruction pipeline 1-2, 1-3 Instruction register B-8 Instruction set

ARM 1-4

ARM formats 1-10 summary 1-9 Thumb 1-4, 1-18 Thumb formats 1-19

Thumb summary 1-20 Instruction set formats 1-9 Instruction speed summary 6-29 Instructions

LDC 4-10

STC 4-10

Index

Internal cycles 3-7 Interrupt disable bits 2-14 Interrupt latencies 2-23

maximum 2-23 minimum 2-23

IRQ mode 2-7

L

LDC 4-10

Link register 2-8

Little-endian 2-4

M

Memory access 1-3 Memory cycle timing summary 3-10 Memory formats 2-4 big-endian 2-4 little-endian 2-4 Merged I-S cycles 3-8

Mode bits 2-15 Modulating MCLK 3-29

N

Nonsequential cycles 3-5

O

Operating modes 2-7 Operating states 2-3

switching states 2-3

P

PC register 2-8 Pipeline 1-3

follower 4-5

Pipelined address timings 3-14 Prefetch Abort B-32 Privileged mode access 3-32 Processor operating states 2-3

Scan chain 0 B-4, B-18 cells B-33

Scan chain 1 B-4, B-19 cells B-37

Scan chain 2 B-4, B-19 Scan chain 3 B-20 Scan chains

implementation B-3 JTAG interface B-3 Sequential access cycle 3-7

Sequential cycles 3-6 Signal descriptions A-3 Signal types 3-3, 4-4, A-2 address class 3-11

Signals

bus interface 3-3

clock and clock control 4-4 coprocessor interface 4-4

Significant address bits 3-12 Simple memory cycle 3-4

SRAM compatible address timing 3-16 STC 4-10

Supervisor Mode 2-7

Undefined instruction trap 1-10 undefined instructions 6-27 Undefined Mode 2-7 Unidirectional bus timing 3-18 Unidirectional data bus 3-18 User Mode 2-7

W

Watchpoint registers B-40 programming and reading B-41

Watchpoints coupling B-52

programming B-47 Word accesses 3-27