Glossary

This glossary describes some of the terms used in this manual. Where terms can have

several meanings, the meaning presented here is intended.

Abort

Is caused by an illegal memory access. Abort can be caused by the external memory

system, an external MMU or the EmbeddedICE Logic.

Addressing modes

A procedure shared by many different instructions, for generating values used by the

instructions. For four of the ARM addressing modes, the values generated are memory

addresses (which is the traditional role of an addressing mode). A fifth addressing mode

generates values to be used as operands by data-processing instructions.

Arithmetic Logic Unit

The part of a computer that performs all arithmetic computations, such as addition and

multiplication, and all comparison operations.

ALU

See Arithmetic Logic Unit.

ARM state

A processor that is executing ARM (32-bit) instructions is operating in ARM state.

Big-endian

Memory organization where the least significant byte of a word is at a higher address

than the most significant byte.

Banked registers

Register numbers whose physical register is defined by the current processor mode. The

banked registers are registers R8 to R14.

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Glossary-1

Breakpoint

A location in the image. If execution reaches this location, the debugger halts execution

of the image.

See also Watchpoint.

CISC

See Complex Instruction Set Computer.

See also Reduced Instruction Set Computer.

CPSR

See Program Status Register.

Control bits

The bottom eight bits of a program status register. The control bits change when an

exception arises and can be altered by software only when the processor is in a

privileged mode.

Current Program Status Register

See Program Status Register

Debug state

A condition that allows the monitoring and control of the execution of a processor.

Usually used to find errors in the application program flow.

Debugger

A debugging system which includes a program, used to detect, locate, and correct

software faults, together with custom hardware that supports software debugging.

EmbeddedICE

The EmbeddedICE Logic is controlled via the JTAG test access port, using a protocol

converter such as MultiICE: an extra piece of hardware that allows software tools to

debug code running on a target processor. See also ICE and JTAG

Exception modes

Privileged modes that are entered when specific exceptions occur.

Exception

Handles an event. For example, an exception could handle an external interrupt or an

undefined instruction.

External abort

An abort that is generated by the external memory system.

FIQ

Fast interrupt.

ICE

See In-circuit emulator.

Idempotent

A mathematical quantity that when applied to itself under a given binary operation

equals itself.

In-circuit emulator

An In-Circuit Emulator (ICE), is a device that aids the debugging of hardware and

software. Debuggable ARM processors such as the ARM7TDMI have extra hardware

called EmbeddedICE to assist this process.

Glossary-2

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IRQ

Interrupt request.

Joint Test Action Group

The name of the organization that developed standard IEEE 1149.1. This standard

defines a boundary-scan architecture used for in-circuit testing of integrated circuit

devices.

JTAG

See Joint Test Action Group.

Link register

This register holds the address of the next instruction after a branch with link

instruction.

Little-endian memory

Memory organization where the most significant byte of a word is at a higher address

than the least significant byte.

LR

See Link register

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system

will comprise several macrocells (such as an ARM7TDMI, an ETM7, and a memory

block) plus application-specific logic.

MMU

See Memory Management Unit

PC

See Program Counter.

Privileged mode

Any processor mode other than User mode. Memory systems typically check memory

accesses from privileged modes against supervisor access permissions rather than the

more restrictive user access permissions. The use of some instructions is also restricted

to privileged modes.

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Glossary-3

See also Program Status Register.

SBO

See Should Be One fields.

SBZ

See Should Be Zero fields.

Should Be One fields

Should be written as one (or all ones for bit fields) by software. Values other than one

produces unpredictable results.

See also Should Be Zero fields.

Should Be Zero fields

Should be written as zero (or all 0s for bit fields) by software. Values other than zero

produce unpredictable results.

See also Should Be One fields.

This instruction enters Supervisor mode to request a particular operating system

function.

SPSR

See Saved Program Status Register.

Stack pointer

A register or variable pointing to the top of a stack. If the stack is full stack the SP points

to the most recently pushed item, else if the stack is empty, the SP points to the first

empty location, where the next item will be pushed.

Status registers

See Program Status Register.

SP

See Stack pointer

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Glossary

SWI

See Software Interrupt Instruction.

TAP

See Test access port.

Test Access Port

The collection of four mandatory and one optional terminals that form the input/output

and control interface to a JTAG boundary-scan architecture. The mandatory terminals

are TDI, TDO, TMS, and TCK. The optional terminal is nTRST.

Thumb instruction

A halfword which specifies an operation for an ARM processor in Thumb state to

perform. Thumb instructions must be halfword-aligned.

Thumb state

A processor that is executing Thumb (16-bit) instructions is operating in Thumb state.

UND

See Undefined.

Undefined

Indicates an instruction that generates an undefined instruction trap.

UNP

See Unpredictable

Unpredictable

Means the result of an instruction cannot be relied upon. Unpredictable instructions

must not halt or hang the processor, or any parts of the system.

Unpredictable fields

Do not contain valid data, and a value can vary from moment to moment, instruction to

instruction, and implementation to implementation.

Watchpoint

A location in the image that is monitored. If the value stored there changes, the debugger

halts execution of the image.

See also Breakpoint.

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Glossary-5

Glossary-6

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