Debug in Depth

B.2 Resetting the TAP controller

The boundary-scan (JTAG) interface includes a state machine controller named the TAP controller. To force the TAP controller into the correct state after power-up, you must apply a reset pulse to the nTRST signal:

•When the boundary-scan interface or EmbeddedICE is to be used, nTRST must be driven LOW and then HIGH again.

•When the boundary-scan interface or EmbeddedICE is not to be used, the nTRST input can be tied permanently LOW.

Note

A clock on TCK is not necessary to reset the device.

The nTRST signal:

1.Selects system mode. This means that the boundary-scan cells do not intercept any of the signals passing between the external system and the core.

2.Selects the IDCODE instruction.

When the TAP controller is put into the SHIFT-DR state and TCK is pulsed, the contents of the ID register are clocked out of TDO.

3.Sets the TAP controller state machine to the TEST-LOGIC RESET state.

4.Sets the scan chain select register to 0x3, which selects the external boundary-scan chain, if present.

Note

You must use nTRST to reset the boundary-scan interface at least once after power up. After this the TAP controller state machine can be put into the TEST-LOGIC RESET state to subsequently reset the boundary-scan interface.

Debug in Depth

B.3 Pullup resistors

The IEEE 1149.1 standard implies that nTRST, TDI, and TMS must have internal pullup resistors. To minimize static current draw, these resistors are not fitted to the ARM7TDMI core. Accordingly, the four inputs to the test interface, the nTRST, TDI, and TMS signal plus TCK, must all be driven to good logic levels to achieve normal circuit operation.

Debug in Depth

B.4 Instruction register

The instruction register is 4 bits in length.

There is no parity bit.

The fixed value 0001 is loaded into the instruction register during the CAPTURE-IR controller state.

The least significant bit of the instruction register is scanned in and scanned out first.