Debug in Depth

B.1 Scan chains and JTAG interface

There are three JTAG-style scan chains within the ARM7TDMI core. These enable debugging and configuration of EmbeddedICE Logic.

A JTAG style Test Access Port (TAP) controller controls the scan chains. For further details of the JTAG specification, refer to IEEE Standard 1149.1 - 1990 Standard Test Access Port and Boundary-Scan Architecture.

In addition, support is provided for an optional fourth scan chain. This is intended to be used for an external boundary-scan chain around the pads of a packaged device. The control signals provided for this scan chain are described in Scan chain 3 on page B-20.

Note

The scan cells are not fully JTAG compliant.

The following sections describe:

•Scan chain implementation

•TAP state machine on page B-5.

B.1.1 Scan chain implementation

The three scan paths are referred to as:

1.Scan chain 0 on page B-4

2.Scan chain 1 on page B-4

3.Scan chain 2 on page B-4.

The scan chains are shown in Figure B-1 on page B-4.

Debug in Depth

Scan chain 0

Figure B-1 ARM7TDMI core scan chain arrangements

Scan chain 0

Scan chain 0 enables access to the entire periphery of the ARM7TDMI core, including the data bus. The scan chain functions enable inter-device testing (EXTEST) and serial testing of the core (INTEST). The order of the scan chain, from search data in to out, is:

1.Data bus bits 0 to 31.

2.The control signals.

3.Address bus bits 31 to 0.

A[0] is scanned out first.

Scan chain 1

Scan chain 1 is a subset of scan chain 0. It provides serial access to the core data bus

D[31:0] and the BREAKPT signal.

There are 33 bits in this scan chain, the order from serial data in to serial data out, is:

1.Data bus bits 0 to 31.

2.The BREAKPT bit, the first to be shifted out.

Scan chain 2

Scan chain 2 enables access to the EmbeddedICE Logic registers. Refer to Test data registers on page B-14 for details.

Debug in Depth

B.1.2 TAP state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure B-2 shows the state transitions that occur in the TAP controller.

Test-Logic Reset

0xF

tms=0

Figure B-2 Test access port controller state transitions

From IEEE Std 1149.1-1990. Copyright 1994-2001 IEEE. All rights reserved.