AC and DC Parameters
7.23Address pipeline control timing
Figure 7-23 shows the ARM7TDMI APE control timing. The timing parameters used in Figure 7-23 are listed in Table 7-22.
MCLK |
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APE |
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A[31:0] |
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Taph |
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Taps |
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nRW |
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Tapeh |
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LOCK |
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nOPC |
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Tape |
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nTRANS |
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MAS[1:0] |
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Figure 7-23 APE control timing
Table 7-22 APE control timing parameters
Symbol |
Parameter |
Parameter |
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type |
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Tape |
MCLKf to address group valid |
Maximum |
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Tapeh |
Address group output hold time from MCLKf |
Minimum |
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Taph |
APE hold time from MCLKf |
Minimum |
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Taps |
APE set up time to MCLKr |
Minimum |
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-27 |
AC and DC Parameters
7.24Notes on AC Parameters
Table 7-23 lists the AC timing parameters in alphabetical order.
Contact your supplier for AC timing parameter values.
In Table 7-23:
•the letter f at the end of a signal name indicates the falling edge
•the letter r at the end of a signal name indicates the rising edge.
Table 7-23 AC timing parameters used in this chapter
Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Tabe |
Address bus enable time |
Maximum |
Figure 7-2 on page 7-6 |
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Tabth |
ABORT hold time from MCLKf |
Minimum |
Figure 7-11 on page 7-15 |
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Tabts |
ABORT set up time to MCLKf |
Minimum |
Figure 7-11 on page 7-15 |
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Tabz |
Address bus disable time |
Maximum |
Figure 7-2 on page 7-6 |
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Taddr |
MCLKr to address valid |
Maximum |
Figure 7-1 on page 7-4 |
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Figure 7-17 on page 7-22 |
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Tah |
Address hold time from MCLKr |
Minimum |
Figure 7-1 on page 7-4 |
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Tald |
Address group latch time |
Maximum |
Figure 7-22 on page 7-26 |
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Tale |
Address group latch open output delay |
Maximum |
Figure 7-22 on page 7-26 |
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Taleh |
Address group latch output hold time |
Minimum |
Figure 7-22 on page 7-26 |
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Tape |
MCLKf to address group valid |
Maximum |
Figure 7-23 on page 7-27 |
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Tapeh |
Address group output hold time from MCLKf |
Minimum |
Figure 7-23 on page 7-27 |
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Taph |
APE hold time from MCLKf |
Minimum |
Figure 7-23 on page 7-27 |
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Taps |
APE set up time to MCLKr |
Minimum |
Figure 7-23 on page 7-27 |
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Tbcems |
BREAKPT to nCPI, nEXEC, nMREQ, SEQ delay |
Maximum |
Figure 7-13 on page 7-17 |
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Tbld |
MCLKr to MAS[1:0] and LOCK |
Maximum |
Figure 7-1 on page 7-4 |
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Tblh |
MAS[1:0] and LOCK hold from MCLKr |
Minimum |
Figure 7-1 on page 7-4 |
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Tbrkh |
Hold time of BREAKPT from MCLKr |
Minimum |
Figure 7-13 on page 7-17 |
7-28 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
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AC and DC Parameters |
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Table 7-23 AC timing parameters used in this chapter (continued) |
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Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Tbrks |
Set up time of BREAKPT to MCLKr |
Minimum |
Figure 7-13 on page 7-17 |
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Tbsch |
TCK high period |
Minimum |
Figure 7-18 on page 7-23 |
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Tbscl |
TCK low period |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsdd |
TCK to data output valid |
Maximum |
Figure 7-18 on page 7-23 |
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Tbsdh |
Data output hold time from TCK |
Minimum |
Figure 7-18 on page 7-23 |
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Tbse |
Output enable time |
Maximum |
Figure 7-20 on page 7-25 |
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Figure 7-21 on page 7-25 |
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Tbsih |
TDI, TMS hold from TCKr |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsis |
TDI, TMS setup to TCKr |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsod |
TCKf to TDO valid |
Maximum |
Figure 7-18 on page 7-23 |
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Tbsoh |
TDO hold time from TCKf |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsr |
nTRST reset period |
Minimum |
Figure 7-19 on page 7-24 |
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Tbssh |
I/O signal setup from TCKr |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsss |
I/O signal setup to TCKr, |
Minimum |
Figure 7-18 on page 7-23 |
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Tbsz |
Output disable time |
Maximum |
Figure 7-20 on page 7-25 |
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Figure 7-21 on page 7-25 |
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Tbylh |
BL[3:0] hold time from MCLKf |
Minimum |
Figure 7-4 on page 7-8 |
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Figure 7-8 on page 7-12 |
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Tbyls |
BL[3:0] set up to from MCLKr |
Minimum |
Figure 7-4 on page 7-8 |
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Figure 7-8 on page 7-12 |
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Tcdel |
MCLK to ECLK delay |
Maximum |
Figure 7-1 on page 7-4 |
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Tclkbs |
TCK to boundary scan clocks |
Maximum |
- |
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Tcommd |
MCLKr to COMMRX, COMMTX valid |
Maximum |
Figure 7-14 on page 7-19 |
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Tcph |
CPA,CPB hold time from MCLKr |
Minimum |
Figure 7-10 on page 7-14 |
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Tcpi |
MCLKf to nCPI valid |
Maximum |
Figure 7-10 on page 7-14 |
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Tcpih |
nCPI hold time from MCLKf |
Minimum |
Figure 7-10 on page 7-14 |
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ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-29 |
AC and DC Parameters
Table 7-23 AC timing parameters used in this chapter (continued)
Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Tcpms |
CPA, CPB to nMREQ, SEQ |
Maximum |
Figure 7-10 on page 7-14 |
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Tcps |
CPA, CPB setup to MCLKr |
Minimum |
Figure 7-10 on page 7-14 |
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Tctdel |
TCK to ECLK delay |
Maximum |
Figure 7-16 on page 7-21 |
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Tcth |
Config hold time |
Minimum |
Figure 7-9 on page 7-13 |
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Tcts |
Config setup time |
Minimum |
Figure 7-9 on page 7-13 |
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Tdbe |
Data bus enable time from DBEr |
Maximum |
Figure 7-5 on page 7-9 |
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Tdbgd |
MCLKr to DBGACK valid |
Maximum |
Figure 7-13 on page 7-17 |
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Tdbgh |
DGBACK hold time from MCLKr |
Minimum |
Figure 7-13 on page 7-17 |
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Tdbgrq |
DBGRQ to DBGRQI valid |
Maximum |
Figure 7-13 on page 7-17 |
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Tdbnen |
DBE to nENOUT valid |
Maximum |
Figure 7-5 on page 7-9 |
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Tdbz |
Data bus disable time from DBEf |
Maximum |
Figure 7-5 on page 7-9 |
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Tdckf |
DCLK induced, TCKf to various outputs valid |
Maximum |
- |
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Tdckfh |
DCLK induced, various outputs hold from TCKf |
Minimum |
- |
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Tdckr |
DCLK induced, TCKr to various outputs valid |
Maximum |
- |
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Tdckrh |
DCLK induced, various outputs hold from TCKr |
Minimum |
- |
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Tdih |
DIN[31:0] hold time from MCLKf |
Minimum |
Figure 7-4 on page 7-8 |
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Tdihu |
DIN[31:0] hold time from MCLKf |
Minimum |
Figure 7-8 on page 7-12 |
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Tdis |
DIN[31:0] setup time to MCLKf |
Minimum |
Figure 7-4 on page 7-8 |
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Tdisu |
DIN[31:0] set up time to MCLKf |
Minimum |
Figure 7-8 on page 7-12 |
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Tdoh |
DOUT[31:0] hold from MCLKf |
Minimum |
Figure 7-3 on page 7-7 |
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Figure 7-5 on page 7-9 |
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Tdohu |
DOUT[31:0] hold time from MCLKf |
Minimum |
Figure 7-7 on page 7-11 |
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Tdout |
MCLKf to D[31:0] valid |
Maximum |
Figure 7-3 on page 7-7 |
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Figure 7-5 on page 7-9 |
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Tdoutu |
MCLKf to DOUT[31:0] valid |
Maximum |
Figure 7-7 on page 7-11 |
7-30 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
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AC and DC Parameters |
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Table 7-23 AC timing parameters used in this chapter (continued) |
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Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Tecapd |
TCK to ECAPCLK changing |
Maximum |
- |
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Texd |
MCLKf to nEXEC valid |
Maximum |
Figure 7-1 on page 7-4 |
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Texh |
nEXEC hold time from MCLKf |
Minimum |
Figure 7-1 on page 7-4 |
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Texth |
EXTERN[1:0] hold time from MCLKf |
Minimum |
Figure 7-13 on page 7-17 |
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Texts |
EXTERN[1:0] set up time to MCLKf |
Minimum |
Figure 7-13 on page 7-17 |
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Tim |
Asynchronous interrupt guaranteed nonrecognition time, with |
Maximum |
Figure 7-11 on page 7-15 |
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ISYNC=0 |
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Tis |
Asynchronous interrupt set up time to MCLKf for guaranteed |
Minimum |
Figure 7-11 on page 7-15 |
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recognition, with ISYNC=0 |
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Tmckh |
MCLK HIGH time |
Minimum |
Figure 7-17 on page 7-22 |
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Tmckl |
MCLK LOW time |
Minimum |
Figure 7-17 on page 7-22 |
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Tmdd |
MCLKr to nTRANS, nM[4:0], and TBIT valid |
Maximum |
Figure 7-1 on page 7-4 |
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Tmdh |
nTRANS and nM[4:0] hold time from MCLKr |
Minimum |
Figure 7-1 on page 7-4 |
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Tmsd |
MCLKf to nMREQ and SEQ valid |
Maximum |
Figure 7-1 on page 7-4 |
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Figure 7-17 on page 7-22 |
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Tmsh |
nMREQ and SEQ hold time from MCLKf |
Minimum |
Figure 7-1 on page 7-4 |
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Tnen |
MCLKf to nENOUT valid |
Maximum |
Figure 7-3 on page 7-7 |
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Figure 7-4 on page 7-8 |
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Figure 7-7 on page 7-11 |
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Figure 7-8 on page 7-12 |
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Tnenh |
nENOUT hold time from MCLKf |
Minimum |
Figure 7-3 on page 7-7 |
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Topcd |
MCLKr to nOPC valid |
Maximum |
Figure 7-1 on page 7-4 |
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Topch |
nOPC hold time from MCLKr |
Minimum |
Figure 7-1 on page 7-4 |
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Trg |
MCLKf to RANGEOUT0, RANGEOUT1 valid |
Maximum |
Figure 7-13 on page 7-17 |
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Trgh |
RANGEOUT0, RANGEOUT1 hold time from MCLKf |
Minimum |
Figure 7-13 on page 7-17 |
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Trm |
Reset guaranteed nonrecognition time |
Maximum |
Figure 7-11 on page 7-15 |
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ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-31 |
AC and DC Parameters
Table 7-23 AC timing parameters used in this chapter (continued)
Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Trqh |
DBGRQ guaranteed non-recognition time |
Minimum |
Figure 7-13 on page 7-17 |
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Trqs |
DBGRQ set up time to MCLKr for guaranteed recognition |
Minimum |
Figure 7-13 on page 7-17 |
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Trs |
Reset setup time to MCLKr for guaranteed recognition |
Minimum |
Figure 7-11 on page 7-15 |
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Trstd |
nRESETf to D[31:0], DBGACK, nCPI, nENOUT, nEXEC, |
Maximum |
Figure 7-19 on page 7-24 |
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nMREQ, SEQ valid |
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Trstl |
nRESET LOW for guaranteed reset |
Minimum |
Figure 7-19 on page 7-24 |
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Trwd |
MCLKr to nRW valid |
Maximum |
Figure 7-1 on page 7-4 |
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Trwh |
nRW hold time from MCLKr |
Minimum |
Figure 7-1 on page 7-4 |
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Tsdtd |
SDOUTBS to TDO valid |
Maximum |
- |
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Tshbsf |
TCK to SHCLKBS, SHCLK2BS falling |
Maximum |
- |
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Tshbsr |
TCK to SHCLKBS, SHCLK2BS rising |
Maximum |
- |
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Tsih |
Synchronous nFIQ, nIRQ hold from MCLKf with ISYNC=1 |
Minimum |
Figure 7-12 on page 7-16 |
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Tsis |
Synchronous nFIQ, nIRQ setup to MCLKf, with ISYNC=1 |
Minimum |
Figure 7-12 on page 7-16 |
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Ttbe |
Address and Data bus enable time from TBEr |
Maximum |
Figure 7-6 on page 7-10 |
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Ttbz |
Address and Data bus disable time from TBEf |
Maximum |
Figure 7-6 on page 7-10 |
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Ttckf |
TCK to TCK1, TCK2 falling |
Maximum |
- |
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Ttckr |
TCK to TCK1, TCK2 rising |
Maximum |
- |
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Ttdbgd |
TCK to DBGACK, DBGRQI changing |
Maximum |
- |
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Ttpfd |
TCKf to TAP outputs |
Maximum |
- |
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Ttpfh |
TAP outputs hold time from TCKf |
Minimum |
- |
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Ttprd |
TCKr to TAP outputs |
Maximum |
- |
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Ttprh |
TAP outputs hold time from TCKr |
Minimum |
- |
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Ttrstd |
nTRSTf to every output valid |
Maximum |
- |
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Ttrstd |
nTRSTf to TAP outputs valid |
Maximum |
- |
7-32 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
|
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AC and DC Parameters |
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Table 7-23 AC timing parameters used in this chapter (continued) |
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Symbol |
Parameter |
Parameter |
Figure cross |
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Type |
reference |
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Ttrsts |
nTRSTr setup to TCKr |
Maximum |
- |
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Twh |
nWAIT hold from MCLKf |
Minimum |
Figure 7-17 on page 7-22 |
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Tws |
nWAIT setup to MCLKr |
Minimum |
Figure 7-17 on page 7-22 |
|
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-33 |