AC and DC Parameters

7.15Debug communications channel output timing

Figure 7-14 shows the ARM7TDMI processor DCC output timing. The timing parameter used in Figure 7-14 is listed in Table 7-14.

MCLK

COMMTX

COMMRX

AC and DC Parameters

7.16Breakpoint timing

Figure 7-15 shows the ARM7TDMI processor synchronous interrupt timing. The timing parameter used in Figure 7-12 on page 7-16 is listed in Table 7-12 on page 7-16.

Figure 7-15 Breakpoint timing

Note

In Figure 7-15, BREAKPT changing in the LOW phase of MCLK (to signal a watchpointed store) affects nCPI, nEXEC, nMREQ, and SEQ in the same phase.

Table 7-15 Breakpoint timing parameters

Symbol Parameter

Parameter type

AC and DC Parameters

7.17Test clock and external clock timing

Figure 7-16 shows the ARM7TDMI processor test clock and external clock timing. The timing parameter used in Figure 7-16 is listed in Table 7-16.

TCK

Tctdel

ECLK

Tctdel

Figure 7-16 TCK and ECLK timing

Note

In Figure 7-16, Tctdel is the delay, on either edge (whichever is greater), from the edge of TCK to ECLK.

Table 7-16 TCK and ECLK timing parameters

AC and DC Parameters

7.18Memory clock timing

Figure 7-17 shows the ARM7TDMI processor memory clock timing. The timing parameters used in Figure 7-17 are listed in Table 7-17.

MCLK

Tmckl Tmckh

nWAIT

ECLK

nMREQ SEQ

Tmsd

A[31:0]

Taddr

Figure 7-17 MCLK timing

Note

In Figure 7-17, the core is not clocked by the HIGH phase of MCLK when nWAIT is LOW. During the cycles shown, nMREQ and SEQ change once, during the first LOW phase of MCLK, and A[31:0] change once, during the second HIGH phase of MCLK. Phase 2 is shown for reference. This is the internal clock from which the core times all its activity. This signal is included to show how the HIGH phase of the external MCLK has been removed from the internal core clock.

Table 7-17 MCLK timing parameters