AC and DC Parameters

7.8Unidirectional data write cycle timing

Figure 7-7 shows the ARM7TDMI processor unidirectional data write cycle timing. The timing parameters used in Figure 7-6 on page 7-10 are listed in Table 7-6 on page 7-10.

MCLK

Tnen

nENOUT

Tdohu

DOUT[31:0]

Tdoutu

Figure 7-7 Unidirectional data write cycle timing

Table 7-7 Unidirectional data write cycle timing parameters

AC and DC Parameters

7.9Unidirectional data read cycle timing

Figure 7-8 shows the ARM7TDMI processor unidirectional data read cycle timing. The timing parameters used in Figure 7-7 on page 7-11 are listed in Table 7-7 on page 7-11.

MCLK

nENOUT

DIN[31:0]

Tdihu

BL[3:0]

Tbylh

Tbyls

Figure 7-8 Unidirectional data read cycle timing

Table 7-8 Unidirectional data read cycle timing parameters

AC and DC Parameters

7.10Configuration pin timing

Figure 7-9 shows the ARM7TDMI processor configuration pin timing. The timing parameters used in Figure 7-9 are listed in Table 7-9.

MCLK

Tcth

BIGEND

Tcts

ISYNC

Tcts

Tcth

Figure 7-9 Configuration pin timing

Table 7-9 Configuration pin timing parameters

AC and DC Parameters

7.11Coprocessor timing

Figure 7-10 shows the ARM7TDMI processor coprocessor timing. The timing parameters used in Figure 7-10 are listed in Table 7-10.

Tcpms

Figure 7-10 Coprocessor timing

Note

In Figure 7-10, usually nMREQ and SEQ become valid Tmsd after the falling edge of MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ depends on Tcpms. Most systems can generate CPA and CPB during the previous phase 2, and so the timing of nMREQ and SEQ is always Tmsd.

Table 7-10 Coprocessor timing parameters