AC and DC Parameters
7.3Address bus enable control
Figure 7-2 shows the ARM7TDMI ABE control timing. The timing parameters used in Figure 7-2 are listed in Table 7-2.
MCLK |
|
ABE |
|
A[31:0] |
|
nRW |
|
LOCK |
|
nOPC |
|
nTRANS |
Tabz |
MAS[1:0] |
Tabe |
Figure 7-2 ABE control timing
Table 7-2 ABE control timing parameters
Symbol |
Parameter |
Parameter type |
|
|
|
Tabe |
Address bus enable time |
Maximum |
Tabz |
Address bus disable time |
Maximum |
7-6 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
AC and DC Parameters
7.4Bidirectional data write cycle
Figure 7-3 shows the ARM7TDMI processor bidirectional data write cycle timing. The timing parameters used in Figure 7-3 are listed in Table 7-3.
MCLK |
|
nENOUT |
|
Tnen |
Tnenh |
D[31:0] |
|
Tdout |
Tdoh |
Figure 7-3 Bidirectional data write cycle timing
Note
In Figure 7-3 DBE is HIGH and nENIN is LOW during the cycle shown.
Table 7-3 Bidirectional data write cycle timing parameters
Symbol |
Parameter |
Parameter type |
|
|
|
Tdoh |
DOUT[31:0] hold from MCLKf |
Minimum |
Tdout |
MCLKf to D[31:0] valid |
Maximum |
Tnen |
MCLKf to nENOUT valid |
Maximum |
Tnenh |
nENOUT hold time from MCLKf |
Minimum |
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-7 |
AC and DC Parameters
7.5Bidirectional data read cycle
Figure 7-4 shows the ARM7TDMI processor bidirectional data read cycle timing. The timing parameters used in Figure 7-4 are listed in Table 7-4.
MCLK
nENOUT
Tnen |
|
|
|
|
Tdih |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
D[31:0]
Tdis
BL[3:0]
Tbylh
Tbyls
Figure 7-4 Bidirectional data read cycle timing
Note
In Figure 7-4, DBE is HIGH and nENIN is LOW during the cycle shown.
Table 7-4 Bidirectional data read cycle timing parameters
Symbol |
Parameter |
Parameter type |
|
|
|
Tbylh |
BL[3:0] hold time from MCLKf |
Minimum |
Tbyls |
BL[3:0] set up to from MCLKr |
Minimum |
Tdih |
DIN[31:0] hold time from MCLKf |
Minimum |
Tdis |
DIN[31:0] setup time to MCLKf |
Minimum |
Tnen |
MCLKf to nENOUT valid |
Maximum |
7-8 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
AC and DC Parameters
7.6Data bus control
Figure 7-5 shows the ARM7TDMI data bus control timing. The timing parameters used in Figure 7-5 are listed in Table 7-5.
MCLK
Tdbnen
nENOUT
Tdbnen
DBE
Tdbz
Tdbe |
|
|
|
|
|
|
|
Tdoh |
|
|
|||||||
|
|
|
|
|
|
D[31:0]
Tdout
nENIN
Tdbz
Tdbe
Figure 7-5 Data bus control timing
Note
The cycle shown in Figure 7-5 is a data write cycle because nENOUT was driven LOW during phase one. Here, DBE has first been used to modify the behavior of the data bus, and then nENIN.
Table 7-5 Data bus control timing parameters
Symbol |
Parameter |
Parameter type |
|
|
|
Tdbe |
Data bus enable time from DBEr |
Maximum |
Tdbnen |
DBE to nENOUT valid |
Maximum |
Tdbz |
Data bus disable time from DBEf |
Maximum |
Tdoh |
DOUT[31:0] hold from MCLKf |
Minimum |
Tdout |
MCLKf to D[31:0] valid |
Maximum |
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
7-9 |
AC and DC Parameters
7.7Output 3-state timing
Figure 7-6 shows the ARM7TDMI processor output 3-state timing. The timing parameters used in Figure 7-6 are listed in Table 7-6.
MCLK |
|
TBE |
|
A[31:0] |
|
D[31:0] |
|
nRW |
|
LOCK |
|
nOPC |
Ttbz |
nTRANS |
|
MAS[1:0] |
Ttbe |
Figure 7-6 Output 3-state timing
Table 7-6 Output 3-state time timing parameters
Symbol |
Parameter |
Parameter type |
|
|
|
Ttbe |
Address and Data bus enable time from TBEr |
Maximum |
Ttbz |
Address and Data bus disable time from TBEf |
Maximum |
7-10 |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |