Chapter 7

AC and DC Parameters

This chapter gives the AC timing parameters of the ARM7TDMI core. It contains the following sections:

•Timing diagram information on page 7-3

•General timing on page 7-4

•Address bus enable control on page 7-6

•Bidirectional data write cycle on page 7-7

•Bidirectional data read cycle on page 7-8

•Data bus control on page 7-9

•Output 3-state timing on page 7-10

•Unidirectional data write cycle timing on page 7-11

•Unidirectional data read cycle timing on page 7-12

•Configuration pin timing on page 7-13

•Coprocessor timing on page 7-14

•Exception timing on page 7-15

•Synchronous interrupt timing on page 7-16

•Debug timing on page 7-17

•Debug communications channel output timing on page 7-19

•Breakpoint timing on page 7-20

AC and DC Parameters

•Test clock and external clock timing on page 7-21

•Memory clock timing on page 7-22

•Boundary scan general timing on page 7-23

•Reset period timing on page 7-24

•Output enable and disable times on page 7-25

•Address latch enable control on page 7-26

•Address pipeline control timing on page 7-27

•Notes on AC Parameters on page 7-28

•DC parameters on page 7-34.

AC and DC Parameters

7.1Timing diagram information

Each timing diagram in this chapter is provided with a table that shows the timing parameters. In the tables:

•the letter f at the end of a signal name indicates the falling edge

•the letter r at the end of a signal name indicates the rising edge.

AC and DC Parameters

7.2General timing

Figure 7-1 shows the ARM7TDMI general timing. The timing parameters used in Figure 7-1 are listed in Table 7-1 on page 7-5.

Figure 7-1 General timing

AC and DC Parameters

Note

In Figure 7-1 on page 7-4, nWAIT, APE, ALE, and ABE are all HIGH during the cycle shown. Tcdel is the delay, on either edge (whichever is greater), from the edge of MCLK to ECLK.

Table 7-1 General timing parameters