Instruction Cycle Timings

6.18Undefined instructions and coprocessor absent

When the processor attempts to execute an instruction that neither it nor a coprocessor can perform (including all undefined instructions) this causes the processor to take the undefined instruction trap.

Cycle timings are listed in Table 6-21 where:

•C represents the current mode-dependent value

•T represents the current state-dependent value.

Table 6-21 Undefined instruction cycle operations

Note

•Coprocessor instructions are not available in Thumb state.

•CPA and CPB are HIGH during the undefined instruction trap.

Instruction Cycle Timings

6.19Unexecuted instructions

Any instruction whose condition code is not met does not execute and adds one cycle to the execution time of the code segment in which it is embedded (see Table 6-22).

Instruction Cycle Timings

6.20Instruction speed summary

Due to the pipelined architecture of the CPU, instructions overlap considerably. In a typical cycle, one instruction can be using the data path while the next is being decoded and the one after that is being fetched. For this reason Table 6-23 presents the incremental number of cycles required by an instruction, rather than the total number of cycles for which the instruction uses part of the processor. Elapsed time, in cycles, for a routine can be calculated from these figures listed in Table 6-23. These figures assume that the instruction is actually executed. Unexecuted instructions take one cycle.

If the condition is not met then all instructions take one S-cycle. The cycle types N, S, I, and C are described in Bus cycle types on page 3-4.

In Table 6-23:

•b is the number of cycles spent in the coprocessor busy-wait loop

•m is:

—1 if bits [32:8] of the multiplier operand are all zero or one

—2 if bits [32:16] of the multiplier operand are all zero or one

—3 if bits [31:24] of the multiplier operand are all zero or all one

•n is the number of words transferred.

Table 6-23 ARM instruction speed summary

Instruction Cycle Timings

Table 6-23 ARM instruction speed summary (continued)