Instruction Cycle Timings

6.15Coprocessor data transfer from coprocessor to memory

The ARM7TDMI processor controls these instructions in the same way as for memory to coprocessor transfers, with the exception that the nRW line is inverted during the transfer cycle.

The cycle timings are listed in Table 6-18 where:

•b represents the busy cycles

•n represents the number of registers.

Table 6-18 coprocessor data transfer instruction cycle operations

Instruction Cycle Timings

Table 6-18 coprocessor data transfer instruction cycle operations (continued)

Note

Coprocessor data transfer operations are not available in Thumb state.

Instruction Cycle Timings

6.16Coprocessor register transfer, load from coprocessor

The busy-wait cycles are similar to those described in Coprocessor data transfer from memory to coprocessor on page 6-21, but the transfer is limited to one word, and the ARM7TDMI core puts the data into the destination register in the third cycle. The third cycle can be merged with the next prefetch cycle into one memory N-cycle as with all processor register load instructions.

The cycle timings are listed in Table 6-19 where:

•b represents the busy cycles.

Table 6-19 Coprocessor register transfer, load from coprocessor

Note

Coprocessor register transfer operations are not available in Thumb state.

Instruction Cycle Timings

6.17Coprocessor register transfer, store to coprocessor

This is the same as described in Coprocessor register transfer, load from coprocessor on page 6-25, except that the last cycle is omitted.

The cycle timings are listed in Table 6-20 where:

•b represents the busy cycles.

Table 6-20 Coprocessor register transfer, store to coprocessor

Note

Coprocessor register transfer operations are not available in Thumb state.