Instruction Cycle Timings

6.11Data swap

This is similar to the load and store register instructions, but the actual swap takes place in the second and third cycles. In the second cycle, the data is fetched from external memory. In the third cycle, the contents of the source register are written out to the external memory. The data read in the second cycle is written into the destination register during the fourth cycle.

LOCK is driven HIGH during the second and third cycles to indicate that both cycles must be allowed to complete without interruption.

The data swapped can be a byte or word quantity. Halfword quantities cannot be specified.

The swap operation can be aborted in either the read or write cycle, and in both cases the destination register is not affected.

The cycle timings are listed in Table 6-14 where:

•s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on page 6-13), s can only represent byte and word transfers. Halfword transfers are not available.

Table 6-14 Data swap instruction cycle operations

Note

The data swap operation is not available in Thumb state.

Instruction Cycle Timings

6.12Software interrupt and exception entry

Exceptions (including software interrupts) force the PC to a particular value and cause the instruction pipeline to be refilled. During the first cycle the forced address is constructed, and a mode change can take place. The return address is moved to R14 and the CPSR to SPSR_svc.

During the second cycle the return address is modified to facilitate return, though this modification is less useful than in the case of the branch with link instruction.

The third cycle is required only to complete the refilling of the instruction pipeline.

The cycle timings are listed in Table 6-15 where:

•pc for:

—software interrupts is the address of the SWI instruction

—Prefetch Aborts is the address of the aborting instruction

—Data Aborts is the address of the instruction following the one which attempted the aborted data transfer

—other exceptions is the address of the instruction following the last one to be executed before entering the exception

•C represents the current mode-dependent value

•T represents the current state-dependent value

•Xn is the appropriate trap address.

Table 6-15 Software Interrupt instruction cycle operations

Instruction Cycle Timings

6.13Coprocessor data operation

A coprocessor data operation is a request from the core for the coprocessor to initiate some action. The action does not have to be completed for some time, but the coprocessor must commit to doing it before driving CPB LOW.

If the coprocessor is not capable of performing the requested task, it must leave CPA and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes LOW.

The cycle timings are listed in Table 6-16 where:

•b represents the busy cycles.

Table 6-16 Coprocessor data operation instruction cycle operations

Note

Coprocessor data operations are not available in Thumb state.

Instruction Cycle Timings

6.14Coprocessor data transfer from memory to coprocessor

For coprocessor transfer instructions from memory the coprocessor must commit to the transfer only when it is ready to accept the data. When CPB goes LOW, the processor produces the addresses and expects the coprocessor to take the data at sequential cycle rates. The coprocessor is responsible for determining the number of words to be transferred, and indicates the last transfer cycle by driving CPA and CPB HIGH.

The ARM7TDMI processor spends the first cycle (and any busy-wait cycles) generating the transfer address, and updates the base address during the transfer cycles.

The cycle timings are listed in Table 6-17 where:

•b represents the busy cycles

•n represents the number of registers.

Table 6-17 Coprocessor data transfer instruction cycle operations

Instruction Cycle Timings

Table 6-17 Coprocessor data transfer instruction cycle operations (continued)

Note

Coprocessor data transfer operations are not available in Thumb state.