Instruction Cycle Timings

6.8Store register

The first cycle of a store register instruction is similar to the first cycle of load register instruction. During the second cycle the base modification is performed, and at the same time the data is written to memory. There is no third cycle.

The cycle timings are listed in Table 6-11 where:

•c represents the current processor mode:

—c=0 for User mode

—c=1 for all other modes

•d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at all other times.

•s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on page 6-13).

Table 6-11 Store register instruction cycle operations

Instruction Cycle Timings

6.9Load multiple registers

The first cycle of the LDM instruction is used to calculate the address of the first word to be transferred, while performing a prefetch from memory. The second cycle fetches the first word, and performs the base modification. During the third cycle, the first word is moved to the appropriate destination register while the second word is fetched from memory, and the modified base is latched internally in case it is needed to restore processor state after an abort. The third cycle is repeated for subsequent fetches until the last data word has been accessed, then the final (internal) cycle moves the last word to its destination register. The cycle timings are listed in Table 6-12.

The last cycle can be merged with the next instruction prefetch to form a single memory N-cycle. If an abort occurs, the instruction continues to completion, but all register modification after the abort is prevented. The final cycle is altered to restore the modified base register (that could have been overwritten by the load activity before the abort occurred).

When the PC is in the list of registers to be loaded the current instruction pipeline must be invalidated.

Note

The PC is always the last register to be loaded, so an abort at any point prevents the PC from being overwritten.

LDM with PC as a destination register is not available in Thumb state. Use

POP{Rlist,PC} to perform the same function.

Table 6-12 Load multiple registers instruction cycle operations

Instruction Cycle Timings

Table 6-12 Load multiple registers instruction cycle operations (continued)

Instruction Cycle Timings

6.10Store multiple registers

The store multiple instruction proceeds very much as load multiple instruction, without the final cycle. The abort handling is much more straightforward as there is no wholesale overwriting of registers.

The cycle timings are listed in Table 6-13 where:

•Ra is the first register specified

•R• are the subsequent registers specified.

Table 6-13 Store multiple registers instruction cycle operations