Instruction Cycle Timings

6.6Multiply and multiply accumulate

The multiply instructions use special hardware that implements integer multiplication with early termination. All cycles except the first are internal

The cycle timings are listed in the following tables:

•multiply instruction cycle operations are listed in Table 6-5

•multiply accumulate instruction cycle operations are listed in Table 6-6

•multiply long instruction cycle operations are listed in Table 6-7 on page 6-10

•multiply accumulate long instruction cycle operations are listed in Table 6-8 on page 6-10.

In Table 6-5 to Table 6-8 on page 6-10:

•m is the number of cycles required by the multiplication algorithm. See

Instruction speed summary on page 6-29.

Table 6-5 Multiply instruction cycle operations

Table 6-6 Multiply accumulate instruction cycle operations

Instruction Cycle Timings

Table 6-6 Multiply accumulate instruction cycle operations (continued)

Table 6-7 Multiply long instruction cycle operations

Table 6-8 Multiply accumulate long instruction cycle operations

Instruction Cycle Timings

Note

The multiply accumulate, multiply long, and multiply accumulate long operations are not available in Thumb state.

Instruction Cycle Timings

6.7Load register

The first cycle of a load register instruction performs the address calculation. During the second cycle the data is fetched from memory and the base register modification is performed, if required. During the third cycle the data is transferred to the destination register, and external memory is unused. This third cycle can normally be merged with the next prefetch cycle to form one memory N-cycle.

Either the base, or destination, or both, can be the PC, and the prefetch sequence is changed if the PC is affected by the instruction.

The data fetch can abort, and in this case the destination modification is prevented. In addition, if the processor is configured for early abort, the base register write-back is also prevented.

The cycle timings are listed in Table 6-9 where:

•c represents the current processor mode:

—c=0 for User mode

—c=1 for all other modes

•d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at all other times

•s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on page 6-13).

Table 6-9 Load register instruction cycle operations

Instruction Cycle Timings

Table 6-9 Load register instruction cycle operations (continued)

Note

Operations where the destination is the PC are not available in Thumb state.

Table 6-10 MAS[1:0] signal encoding