Instruction Cycle Timings

6.3Thumb branch with link

A Thumb Branch with Link operation consists of two consecutive Thumb instructions. Refer to the ARM Architecture Reference Manual for more information.

The first instruction acts like a simple data operation to add the PC to the upper part of the offset, storing the result in Register 14, LR.

The second instruction which takes a single cycle acts in a similar fashion to the ARM state branch with link instruction. The first cycle therefore calculates the final branch destination whilst performing a prefetch from the current PC.

The second cycle of the second instruction performs a fetch from the branch destination and the return address is stored in R14.

The third cycle of the second instruction performs a fetch from the destination +2, refilling the instruction pipeline and R14 is modified, with 2 subtracted from it, to simplify the return to MOV PC, R14. This makes the PUSH {..,LR} ; POP {..,PC} type of subroutine work correctly.

The cycle timings of the complete operation are listed in Table 6-2 where:

•pc is the address of the first instruction of the operation.

Table 6-2 Thumb long branch with link

Instruction Cycle Timings

6.4Branch and Exchange

A Branch and Exchange (BX) operation takes three cycles and is similar to a branch. In the first cycle, the branch destination and the new core state are extracted from the register source, whilst performing a prefetch from the current PC. This prefetch is performed in all cases, since by the time the decision to take the branch has been reached, it is already too late to prevent the prefetch.

During the second cycle, a fetch is performed from the branch destination address using the new instruction width, dependent on the state that has been selected.

The third cycle performs a fetch from the destination address +2 or +4 (dependent on the new specified state), refilling the instruction pipeline.

The cycle timings are listed in Table 6-3 where:

•W and w represent the instruction width before and after the BX respectively. The width equals four bytes in ARM state and two bytes in Thumb state. For example, when changing from ARM to Thumb state, W equals four and w equals two

•I and i represent the memory access size before and after the BX respectively. MAS[1:0] equals two in ARM state and one in Thumb state. When changing from Thumb to ARM state, I equals one and i equals two.

•T and t represent the state of the TBIT before and after the BX respectively. TBIT equals 0 in ARM state and 1 in Thumb state. When changing from ARM to Thumb state, T equals 0 and t equals 1.

Table 6-3 Branch and exchange instruction cycle operations

Instruction Cycle Timings

6.5Data operations

A data operation executes in a single datapath cycle unless a shift is determined by the contents of a register. A register is read onto the A bus, and a second register or the immediate field onto the B bus (see Figure 1-3 on page 1-7). The ALU combines the A bus source and the shifted B bus source according to the operation specified in the instruction, and the result, when required, is written to the destination register.

Note

Compare and test operations do not produce results. Only the ALU status flags are affected.

An instruction prefetch occurs at the same time as the data operation, and the program counter is incremented.

When the shift length is specified by a register, an additional datapath cycle occurs during this cycle. The data operation occurs on the next cycle which is an internal cycle that does not access memory. This internal cycle can be merged with the following sequential access by the memory manager as the address remains stable through both cycles.

The PC can be one or more of the register operands. When it is the destination, external bus activity can be affected. If the result is written to the PC, the contents of the instruction pipeline are invalidated, and the address for the next instruction prefetch is taken from the ALU rather than the address incrementer. The instruction pipeline is refilled before any further execution takes place, and during this time exceptions are ignored.

PSR transfer operations (MSR and MRS) exhibit the same timing characteristics as the data operations except that the PC is never used as a source or destination register.

The cycle timings are listed in Table 6-4 on page 6-8 where:

•pc is the address of the branch instruction

•alu is the destination address calculated by the ARM7TDMI core

•(alu) is the contents of that address.

Instruction Cycle Timings

Table 6-4 Data operation instruction cycles

Note

The shifted register operations where the destination is the PC are not available in

Thumb state.